diff --git a/gm_soc_rfsoc_top_sw.slx b/gm_soc_rfsoc_top_sw.slx
index ab6feef..0a47354 100644
Binary files a/gm_soc_rfsoc_top_sw.slx and b/gm_soc_rfsoc_top_sw.slx differ
diff --git a/referencedmodels/soc_rfsoc_fpga.slx b/referencedmodels/soc_rfsoc_fpga.slx
index e2a1dbb..d4b62b5 100644
Binary files a/referencedmodels/soc_rfsoc_fpga.slx and b/referencedmodels/soc_rfsoc_fpga.slx differ
diff --git a/referencedmodels/soc_rfsoc_proc.slx b/referencedmodels/soc_rfsoc_proc.slx
index fde9272..afc65c5 100644
Binary files a/referencedmodels/soc_rfsoc_proc.slx and b/referencedmodels/soc_rfsoc_proc.slx differ
diff --git a/soc_rfsoc_top.slx b/soc_rfsoc_top.slx
index d053d1a..8b81f5a 100644
Binary files a/soc_rfsoc_top.slx and b/soc_rfsoc_top.slx differ
diff --git a/utilities/soc_rfsoc_init.m b/utilities/soc_rfsoc_init.m
index 5080e30..45fb8a9 100644
--- a/utilities/soc_rfsoc_init.m
+++ b/utilities/soc_rfsoc_init.m
@@ -49,12 +49,12 @@ pulseGenGain = 1;
 %% Software parameters
 
 % Signal generator update rate
-TsSW = 0.25;
+TsSW = 0.001;
 
 %% Simulation parameters
 
 % Sim run time
-stoptime = TsFPGA*(9 + 1*348 + 1 + 2*128 + 1); %10*TsSW; %TsFPGA*(1*128+348)
+%stoptime = TsFPGA*(9 + 1*348 + 1 + 2*128 + 1); %10*TsSW; %TsFPGA*(1*128+348)
 
 %% Channelizer parameters