docs: update documentation for capture redesign and validation

README.md

@@ -11,21 +11,34 @@ The system implements a high-throughput signal chain in the FPGA (PL) and perfor
 ## Current Status
 
 - Tx subsystem: LFM pulse generator (DDS-based, complex output)
-- Rx subsystem: fully functional channelizer pipeline (PFB-based)
+- Rx subsystem: fully functional channelizer pipeline (PFB-based) or bypass
 - PL → PS interface: AXI4-Stream + DMA operational
-- PS processing: frame-based algorithm (RMS + peak detection)
+- PS processing: frame-based algorithm on a Data Process Window (DPW)
 
 ---
 
 ## System Architecture
 
-ADC → Channelizer (PFB, 512 bins)  
-→ FFT_Capture (frame control)  
-→ FIFO Serializer (4 FIFOs → 1 stream)  
-→ AXI4-Stream (uint64)  
+Tx (PL)  
+→ Waveform Generator (LFM / CW / Pulsed)  
+→ DAC  
+→ RF Loopback / Input  
+
+Rx (PL)   
+→ ADC  
+→ Channelizer (PFB, 512 bins) / Bypass / Counter  
+→ Capture (frame control)  
+→ AXI4-Stream (128-bit, 4 samples/clock)  
 → DMA (S2MM)  
 → PS Memory  
-→ Processor Algorithm  
+→ Processor Algorithm
+
+Post Processing (PS)  
+→ Triggered Capture  
+→ Sample Unpacking (I/Q)  
+→ Data Reshaping → [FrameSize x nFrames x nTriggers]  
+→ Host Communication / Processing / Visualization
+→ One DPW is a windows of FrameSize x nFrames samples
 
 ---