From 261984b30f915c859dbe890f85a0646d71f6ae6b Mon Sep 17 00:00:00 2001 From: canisio Date: Thu, 2 Jul 2026 16:04:00 -0300 Subject: [PATCH] update diagram (added Simulink) --- docs/img/resm_diagram.drawio | 89 +++++++++++++++++++++++------------- docs/img/resm_diagram.svg | 2 +- 2 files changed, 59 insertions(+), 32 deletions(-) diff --git a/docs/img/resm_diagram.drawio b/docs/img/resm_diagram.drawio index a59b118..0e638d7 100644 --- a/docs/img/resm_diagram.drawio +++ b/docs/img/resm_diagram.drawio @@ -1,15 +1,20 @@ - + - + + + + + + - + - + @@ -17,14 +22,14 @@ - + - - + + - - + + @@ -32,19 +37,19 @@ - - + + - - + + - + - + - - + + @@ -52,8 +57,8 @@ - - + + @@ -81,13 +86,13 @@ - + - + @@ -162,8 +167,8 @@ - - + + @@ -173,23 +178,23 @@ - + - - + + - + - + - + @@ -197,12 +202,34 @@ - + - + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/img/resm_diagram.svg b/docs/img/resm_diagram.svg index 9cd7137..7e7c4b0 100644 --- a/docs/img/resm_diagram.svg +++ b/docs/img/resm_diagram.svg @@ -1,3 +1,3 @@ -
I - 16bits
RF LOOPBACK
DAC
Data clock = 128MHz
4 Samples/clock
BW = 512MHz
Interpolation = 8X
Fs = 4096MHz
ADC
Fs = 4096MHz
Decimation = 8X
BW = 512MHz
4 Samples/clock
Data clock = 128MHz
Q - 16bits
PL
Tx Subsystem
Pulsed LFM Generator
Rx Subsystem
Debug Counter
PFB 512 Channels
Bypass
512 Samples
DPW capture
N frames of 512 samples
I - 16bits
Q - 16bits
Shared Memory
DMA Engine
AXI-Stream to
 AXI-MM
AXI-Lite
Memory Mapped
Registers
PS
Parameters
  • Initialization
  • Configuration
  • Capture Control
Data Processing
  • Unpack samples
  • Convert to complex type
  • Reshape to DPW Matrix
  • Processing algorithm
CONTROL
CONFIG
\ No newline at end of file +
ZCU111-RFSoC
I - 16bits
RF LOOPBACK
DAC
Data clock = 128MHz
4 Samples/clock
BW = 512MHz
Interpolation = 8X
Fs = 4096MHz
ADC
Fs = 4096MHz
Decimation = 8X
BW = 512MHz
4 Samples/clock
Data clock = 128MHz
Q - 16bits
PL
Tx Subsystem
Pulsed LFM Generator
Rx Subsystem
Debug Counter
PFB 512 Channels
Bypass
512 Samples
DPW capture
N frames of 512 samples
I - 16bits
Q - 16bits
Shared Memory
DMA Engine
AXI-Stream to
 AXI-MM
AXI-Lite
Memory Mapped
Registers
PS
Parameters
  • Initialization
  • Configuration
  • Capture Control
Data Processing
  • DPW periodic read
  • Unpack samples
  • Convert to complex type
  • Reshape to DPW Matrix
  • Processing algorithm
CONTROL
CONFIG


TCP-IP
Simulink
Parameters
  • Constants
  • Switches
  • Slides
  • Gains
Data Visualization
  • Spectrum viewer
  • Array plot
  • Time scope
\ No newline at end of file