From 29a5afbf7e7d481da4c3447cba05634369b2c270 Mon Sep 17 00:00:00 2001 From: canisio Date: Fri, 26 Jun 2026 13:43:42 -0300 Subject: [PATCH] updated diagram (PL side ok) --- docs/img/resm_diagram.svg | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/img/resm_diagram.svg b/docs/img/resm_diagram.svg index fb1fbbd..714d212 100644 --- a/docs/img/resm_diagram.svg +++ b/docs/img/resm_diagram.svg @@ -1,3 +1,4 @@ + -
I - 16bits
RF LOOPBACK
DAC
Data clock = 128MHz
4 Samples/clock
BW = 512MHz
Interpolation = 8X
Fs = 4096MHz
ADC
Fs = 4096MHz
Decimation = 8X
BW = 512MHz
4 Samples/clock
Data clock = 128MHz
Q - 16bits
PL
Tx Subsystem
Pulsed LFM Generator
Rx Subsystem
Debug Counter
PFB 512 Channels
Bypass
512 Samples
DPW capture
N frames of 512 samples
I - 16bits
Q - 16bits
\ No newline at end of file +
I - 16bits
RF LOOPBACK
DAC
Data clock = 128MHz
4 Samples/clock
BW = 512MHz
Interpolation = 8X
Fs = 4096MHz
ADC
Fs = 4096MHz
Decimation = 8X
BW = 512MHz
4 Samples/clock
Data clock = 128MHz
Q - 16bits
PL
Tx Subsystem
Pulsed LFM Generator
Rx Subsystem
Debug Counter
PFB 512 Channels
Bypass
512 Samples
DPW capture
N frames of 512 samples
I - 16bits
Q - 16bits
\ No newline at end of file