diff --git a/docs/img/resm_diagram.drawio b/docs/img/resm_diagram.drawio index caa1aee..a59b118 100644 --- a/docs/img/resm_diagram.drawio +++ b/docs/img/resm_diagram.drawio @@ -1,15 +1,15 @@ - + - + - + - + @@ -17,14 +17,14 @@ - + - - + + - - + + @@ -32,16 +32,19 @@ - - + + - + - + - - + + + + + @@ -50,11 +53,11 @@ - - + + - + @@ -62,6 +65,11 @@ + + + + + @@ -129,24 +137,24 @@ - + - + - + - + - + - - + + @@ -154,6 +162,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/img/resm_diagram.svg b/docs/img/resm_diagram.svg index 714d212..9cd7137 100644 --- a/docs/img/resm_diagram.svg +++ b/docs/img/resm_diagram.svg @@ -1,4 +1,3 @@ - -
I - 16bits
RF LOOPBACK
DAC
Data clock = 128MHz
4 Samples/clock
BW = 512MHz
Interpolation = 8X
Fs = 4096MHz
ADC
Fs = 4096MHz
Decimation = 8X
BW = 512MHz
4 Samples/clock
Data clock = 128MHz
Q - 16bits
PL
Tx Subsystem
Pulsed LFM Generator
Rx Subsystem
Debug Counter
PFB 512 Channels
Bypass
512 Samples
DPW capture
N frames of 512 samples
I - 16bits
Q - 16bits
\ No newline at end of file +
I - 16bits
RF LOOPBACK
DAC
Data clock = 128MHz
4 Samples/clock
BW = 512MHz
Interpolation = 8X
Fs = 4096MHz
ADC
Fs = 4096MHz
Decimation = 8X
BW = 512MHz
4 Samples/clock
Data clock = 128MHz
Q - 16bits
PL
Tx Subsystem
Pulsed LFM Generator
Rx Subsystem
Debug Counter
PFB 512 Channels
Bypass
512 Samples
DPW capture
N frames of 512 samples
I - 16bits
Q - 16bits
Shared Memory
DMA Engine
AXI-Stream to
 AXI-MM
AXI-Lite
Memory Mapped
Registers
PS
Parameters
  • Initialization
  • Configuration
  • Capture Control
Data Processing
  • Unpack samples
  • Convert to complex type
  • Reshape to DPW Matrix
  • Processing algorithm
CONTROL
CONFIG
\ No newline at end of file