Added block diagram of the system
This commit is contained in:
canisio
143
docs/img/resm_diagram.drawio
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143
docs/img/resm_diagram.drawio
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<mxCell id="MkqXqfyG2YaBNjo1GXRg-9" parent="MkqXqfyG2YaBNjo1GXRg-5" style="rounded=1;whiteSpace=wrap;html=1;" value="Bypass<div>512 Samples</div>" vertex="1">
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<mxCell id="MkqXqfyG2YaBNjo1GXRg-10" parent="1" style="rounded=1;whiteSpace=wrap;html=1;" value="DAC<div>Data clock = 128MHz</div><div>4 Samples/clock</div><div>BW = 512MHz</div><div>Interpolation = 8X</div><div>Fs = 4096MHz</div>" vertex="1">
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</mxCell>
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<mxCell id="MkqXqfyG2YaBNjo1GXRg-12" parent="1" style="rounded=1;whiteSpace=wrap;html=1;" value="ADC<div>Fs = 4096MHz</div><div>Decimation = 8X</div><div>BW = 512MHz</div><div>4 Samples/clock</div><div>Data clock = 128MHz</div>" vertex="1">
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</mxGraphModel>
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</diagram>
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