diff --git a/referencedmodels/soc_rfsoc_fpga.slx b/referencedmodels/soc_rfsoc_fpga.slx
index df8e6e8..7779e59 100644
Binary files a/referencedmodels/soc_rfsoc_fpga.slx and b/referencedmodels/soc_rfsoc_fpga.slx differ
diff --git a/referencedmodels/soc_rfsoc_proc.slx b/referencedmodels/soc_rfsoc_proc.slx
index 76520bc..25d1ae8 100644
Binary files a/referencedmodels/soc_rfsoc_proc.slx and b/referencedmodels/soc_rfsoc_proc.slx differ
diff --git a/soc_rfsoc_top.slx b/soc_rfsoc_top.slx
index c2782ae..903a240 100644
Binary files a/soc_rfsoc_top.slx and b/soc_rfsoc_top.slx differ
diff --git a/utilities/soc_rfsoc_init.m b/utilities/soc_rfsoc_init.m
index ac1fa30..d0d9e5b 100644
--- a/utilities/soc_rfsoc_init.m
+++ b/utilities/soc_rfsoc_init.m
@@ -40,13 +40,16 @@ PRI = 1/PRF;
 % CW mode (bypass pulse generation)
 CwMode = true;
 
+% Counter mode (bypass pulse and CW generation)
+CounterMode = true;
+
 % Output gain
 pulseGenGain = 1;
 
 %% Software parameters
 
 % Signal generator update rate
-TsSW = 0.25;
+TsSW = 0.0025;
 
 %% Simulation parameters