diff --git a/docs/img/resm_diagram.drawio b/docs/img/resm_diagram.drawio index e331b6d..caa1aee 100644 --- a/docs/img/resm_diagram.drawio +++ b/docs/img/resm_diagram.drawio @@ -1,6 +1,6 @@ - + @@ -17,72 +17,28 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - + + + + - + - + - + @@ -93,13 +49,93 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -107,10 +143,10 @@ - + - - + + @@ -118,25 +154,6 @@ - - - - - - - - - - - - - - - - - - - diff --git a/docs/img/resm_diagram.svg b/docs/img/resm_diagram.svg index 90ea91d..fb1fbbd 100644 --- a/docs/img/resm_diagram.svg +++ b/docs/img/resm_diagram.svg @@ -1,3 +1,3 @@ -
I - 16bits
Tx Subsystem
Pulsed LFM Generator
Rx Subsystem
Debug Counter
PFB 512 Channels
Bypass
512 Samples
DPW capture
N frames of 512 samples
RF LOOPBACK
DAC
Data clock = 128MHz
4 Samples/clock
BW = 512MHz
Interpolation = 8X
Fs = 4096MHz
ADC
Fs = 4096MHz
Decimation = 8X
BW = 512MHz
4 Samples/clock
Data clock = 128MHz
Q - 16bits
I - 16bits
Q - 16bits
\ No newline at end of file +
I - 16bits
RF LOOPBACK
DAC
Data clock = 128MHz
4 Samples/clock
BW = 512MHz
Interpolation = 8X
Fs = 4096MHz
ADC
Fs = 4096MHz
Decimation = 8X
BW = 512MHz
4 Samples/clock
Data clock = 128MHz
Q - 16bits
PL
Tx Subsystem
Pulsed LFM Generator
Rx Subsystem
Debug Counter
PFB 512 Channels
Bypass
512 Samples
DPW capture
N frames of 512 samples
I - 16bits
Q - 16bits
\ No newline at end of file