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cleaned up log signals (still not working)

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canisio
2026-04-07 09:26:50 -03:00
parent fdde9ec62b
commit 5a3bc8891d
3 changed files with 1 additions and 30 deletions
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referencedmodels/soc_rfsoc_fpga.slx
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soc_rfsoc_top.slx
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29
utilities/soc_rfsoc_init.m
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@@ -76,32 +76,3 @@ nFrames = nChan/SamplesPerCycle;
% Frame size after serializing x2 % Frame size after serializing x2
%frameSize = SamplesPerCycle/2; %frameSize = SamplesPerCycle/2;
% function soc_rfsoc_init(mdlPath)
% % Initialization fcn for the model. It sets the model-wide params
% % which are derived based on sample rate.
%
% % 'FrameSize and 'NumBuffers' variables are set during model
% % PreLoadFcn callback into base workspace. These two variables should be
% % changed directly at the MATLAB command
%
% % FrameSize = evalin('base','FrameSize');
%
% dacSampleRate = get_param([mdlPath '/RF Data Converter'], 'dacSampleRate');
% dacSampleRate = evalin('base', dacSampleRate)*1e6;
% dacSamplesPerCycle = str2double(get_param([mdlPath '/RF Data Converter'], 'dacSamplesPerCycle'));
% dacInterpolationMode = str2double(get_param([mdlPath '/RF Data Converter'], 'interpolationMode'));
% streamClkFrequency = dacSampleRate/(dacSamplesPerCycle*dacInterpolationMode);
%
% SampleTime = 1/streamClkFrequency;
%
% % derived model-wide variables set into base workspace.
% assignin('base','FPGAClkRate', streamClkFrequency);
% assignin('base','TsFPGA', SampleTime);
% assignin('base','SamplesPerCycle', dacSamplesPerCycle);
% assignin('base','IntDecFactor', dacInterpolationMode);
% end