Removed RMS and Fmax outputs

Formatted top diagrams

utilities/soc_rfsoc_init.m

@@ -42,20 +42,24 @@ pulseT = 10e-6;
 %CwMode = false;
 
 % Counter mode (bypass pulse and CW generation)
-CounterMode = true;
+%CounterMode = true;
 
 % Output gain
 pulseGenGain = 1;
 
-%% Software parameters
+%% Simulation/External Mode parameters (conditional)
+bd = bdroot; % Retrive which model is calling this function
 
-% Signal generator update rate
-TsSW = 0.5;
-
-%% Simulation parameters
-
-% Sim run time
-%stoptime = TsFPGA*(9 + 1*348 + 1 + 2*128 + 1); %10*TsSW; %TsFPGA*(1*128+348)
+switch bd
+    case 'soc_rfsoc_top'
+        TsSW = 0.0005; % Signal generator and capture update rate
+        StopTime = 0.0025; % Simulation total time
+    case 'gm_soc_rfsoc_top_sw'
+        TsSW = 0.5;
+        StopTime = 10;
+    otherwise
+        error('rfsoc_init: InvalidModel (%s not supported).', bd);
+end
 
 %% Channelizer parameters