4 dalay on the signals of bypass to align test counter to frame start. Appears to be working. Test on board.

2026-04-22 10:30:14 -03:00
parent 6098d86851
commit 9a0404f1a9
4 changed files with 2 additions and 2 deletions
--- a/referencedmodels/soc_rfsoc_fpga.slx
+++ b/referencedmodels/soc_rfsoc_fpga.slx
--- a/referencedmodels/soc_rfsoc_proc.slx
+++ b/referencedmodels/soc_rfsoc_proc.slx
--- a/soc_rfsoc_top.slx
+++ b/soc_rfsoc_top.slx
--- a/utilities/soc_rfsoc_init.m
+++ b/utilities/soc_rfsoc_init.m
@@ -24,7 +24,7 @@ NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);
 %% Test signal parameters

 % Pulse width
-pulseWidth = 1;%4e-6;
+pulseWidth = 0.001;%4e-6;

 % Pulse start/end frequencies
 pulseCentFreq = 0e6;
@@ -49,7 +49,7 @@ pulseGenGain = 1;
 %% Software parameters

 % Signal generator update rate
-TsSW = 0.001;
+TsSW = 0.25;

 %% Simulation parameters