canisio/Zcu111ResmReceiver
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Replace serializer with 128-bit packer and add MultiFrameCapture (testbench)

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Removed FIFO serializer and implemented 128-bit AXI packing (4 samples/beat)
Added initial MultiFrameCapture FSM
Validated with counter input
Sine/channelizer validation pending (frame interpretation update needed)
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canisio
2026-04-14 17:56:57 -03:00
parent aad231b55a
commit 9fd110f451
2 changed files with 1 additions and 1 deletions
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utilities/soc_rfsoc_init.m
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@@ -51,7 +51,7 @@ TsSW = 0.5e-3;
%% Simulation parameters
% Sim run time
stoptime = TsFPGA*(9+348+3+38+4*128); %10*TsSW; %TsFPGA*(1*128+348)
stoptime = TsFPGA*(358 + 10*128); %10*TsSW; %TsFPGA*(1*128+348)
%% Channelizer parameters