Replace serializer with 128-bit packer and add MultiFrameCapture (testbench)

Removed FIFO serializer and implemented 128-bit AXI packing (4 samples/beat)
Added initial MultiFrameCapture FSM
Validated with counter input
Sine/channelizer validation pending (frame interpretation update needed)

utilities/soc_rfsoc_init.m

@@ -51,7 +51,7 @@ TsSW = 0.5e-3;
 %% Simulation parameters
 
 % Sim run time
-stoptime = TsFPGA*(9+348+3+38+4*128); %10*TsSW; %TsFPGA*(1*128+348)
+stoptime = TsFPGA*(358 + 10*128); %10*TsSW; %TsFPGA*(1*128+348)
 
 %% Channelizer parameters