diff --git a/docs/pl_rx_subsystem.md b/docs/pl_rx_subsystem.md
index 66d09bc..766091c 100644
--- a/docs/pl_rx_subsystem.md
+++ b/docs/pl_rx_subsystem.md
@@ -8,12 +8,16 @@
 
 The Rx subsystem implements a **polyphase filter bank (PFB) channelizer** followed by FFT processing.
 
-It converts wideband ADC input into frequency-domain channels.
+It converts wideband ADC input into frequency-domain channels and streams the result to the PS.
+
+A **bypass path** is also available for raw data inspection and debugging.
 
 ---
 
 ## Architecture
 
+### Channelizer Path (default)
+
 ADC
  ↓
 PFB Channelizer (Decimation + Filtering)
@@ -30,7 +34,55 @@ DMA
 
 ---
 
-## Processing Chain
+### Bypass Path (Debug / Raw Data)
+
+ADC
+ ↓
+Bypass Path
+ ↓
+FIFO / Serializer
+ ↓
+AXI4-Stream
+ ↓
+DMA
+
+---
+
+## Bypass Functionality
+
+The bypass allows direct observation of the input signal without channelization.
+
+### Purpose
+
+- Debugging and validation
+- Access to raw ADC-domain data
+- Comparison with channelized output
+- Verification of downstream processing
+
+---
+
+### Behavior
+
+- Input data is routed directly to output
+- No filtering or FFT applied
+- Maintains same output interface (AXI4-Stream)
+
+---
+
+### Selection Mechanism
+
+A selector signal chooses between:
+
+- Channelizer output (normal operation)
+- Bypass output (raw data)
+
+Implementation typically uses:
+- Parallel paths
+- Output switching logic
+
+---
+
+## Processing Chain (Channelizer Mode)
 
 ### ADC Input
 - Sampling rate: 4096 MSPS
@@ -71,7 +123,7 @@ DMA
 - Fully streaming pipeline
 - High throughput
 - Deterministic latency
-- DMA-ready output
+- Supports dual-mode operation (channelizer / bypass)
 
 ---