Multi-frame capture integrated into full design with trigger-controlled DPW; AXI stream (uint32 [4x1]) and DMA framing aligned; fixed FSM termination condition (no overflow); validated end-to-end (PL→DMA→PS) using counter input for multiple nFrames

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canisio

2026-04-17 17:03:34 -03:00

parent fc50e71ab5

commit b2ce956f41

5 changed files with 2 additions and 2 deletions

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