Multi-frame capture integrated into full design with trigger-controlled DPW; AXI stream (uint32 [4x1]) and DMA framing aligned; fixed FSM termination condition (no overflow); validated end-to-end (PL→DMA→PS) using counter input for multiple nFrames

2026-04-17 17:03:34 -03:00
parent fc50e71ab5
commit b2ce956f41
5 changed files with 2 additions and 2 deletions
--- a/block_capture/TBm_capture.slx
+++ b/block_capture/TBm_capture.slx
--- a/referencedmodels/soc_rfsoc_fpga.slx
+++ b/referencedmodels/soc_rfsoc_fpga.slx
--- a/referencedmodels/soc_rfsoc_proc.slx
+++ b/referencedmodels/soc_rfsoc_proc.slx
--- a/soc_rfsoc_top.slx
+++ b/soc_rfsoc_top.slx
--- a/utilities/soc_rfsoc_init.m
+++ b/utilities/soc_rfsoc_init.m
@@ -46,7 +46,7 @@ pulseGenGain = 1;
 %% Software parameters

 % Signal generator update rate
-TsSW = 0.00025;
+TsSW = 0.0025;

 %% Simulation parameters

@@ -75,7 +75,7 @@ channelizerCoeffs = channelizer.coeffs.Numerator;
 %chanFStart = chanBW/2:chanBW:(fs/2-chanBW/2);

 %Number of frames in the DPW
-nFrames = 1;%nChan/SamplesPerCycle;
+nFrames = 8;%nChan/SamplesPerCycle;

 % Frame size after serializing x2
 %frameSize = SamplesPerCycle/2;