diff --git a/gm_soc_rfsoc_top_sw.slx b/gm_soc_rfsoc_top_sw.slx
index 1ef0694..03011f8 100644
Binary files a/gm_soc_rfsoc_top_sw.slx and b/gm_soc_rfsoc_top_sw.slx differ
diff --git a/utilities/soc_rfsoc_postload.m b/utilities/soc_rfsoc_postload.m
index 48c67ae..90504d7 100644
--- a/utilities/soc_rfsoc_postload.m
+++ b/utilities/soc_rfsoc_postload.m
@@ -1,5 +1,10 @@
+%% Check if top model is loaded
+if ~bdIsLoaded('soc_rfsoc_top')
+    load_system('soc_rfsoc_top');
+end
+
 %% Get parameters configured on the block 
-IntDecFactor = str2double(get_param([bdroot '/RF Data Converter'], ...
+IntDecFactor = str2double(get_param(['soc_rfsoc_top' '/RF Data Converter'], ...
     'interpolationMode')); % Interpolation and decimation factor
-SamplesPerCycle = str2double(get_param([bdroot '/RF Data Converter'], ...
+SamplesPerCycle = str2double(get_param(['soc_rfsoc_top' '/RF Data Converter'], ...
     'dacSamplesPerCycle')); % samples per FPGA cycle
\ No newline at end of file