Validate 16-bit Q1.15 Rx chain (baseline, partial validation)

Standardized ADC/DAC and channelizer input to fixdt(1,16,15) Rescaled channelizer output from sFix25_En23 to 16-bit complex Verified channelizer path and spectrum behavior in full simulation Bypass path and datatype tuning (coefficients/output) pending validation
2026-04-13 17:47:08 -03:00
parent f221e14c2c
commit ccc6b9cd73
4 changed files with 1 additions and 1 deletions
--- a/referencedmodels/soc_rfsoc_fpga.slx
+++ b/referencedmodels/soc_rfsoc_fpga.slx
--- a/referencedmodels/soc_rfsoc_proc.slx
+++ b/referencedmodels/soc_rfsoc_proc.slx
--- a/soc_rfsoc_top.slx
+++ b/soc_rfsoc_top.slx
--- a/utilities/soc_rfsoc_init.m
+++ b/utilities/soc_rfsoc_init.m
@@ -28,7 +28,7 @@ pulseWidth = 4e-6;

 % Pulse start/end frequencies
 pulseCentFreq = 100e6;
-pulseBw = 5e6; % Pulse bandwidth
+pulseBw = 0e6; % Pulse bandwidth

 % Number of pulses
 numPulses = 10;