Added documentation and updated README

README.md

@@ -4,81 +4,63 @@
 
 This project is based on the RFSoC SoC Blockset reference design, adapted as a prototype for a Radar Electronic Support Measures (R-ESM) receiver.
 
-### Current Status
+The system implements a high-throughput signal chain in the FPGA (PL) and performs frame-based processing in the processor (PS).
 
-- Tx subsystem: simple tone generator (to be replaced by LFM pulse generator)
+---
+
+## Current Status
+
+- Tx subsystem: LFM pulse generator (DDS-based, complex output)
 - Rx subsystem: fully functional channelizer pipeline (PFB-based)
-- PL → PS interface: AXI4-Stream + DMA working
+- PL → PS interface: AXI4-Stream + DMA operational
 - PS processing: frame-based algorithm (RMS + peak detection)
 
 ---
 
 ## System Architecture
 
-ADC → Channelizer (PFB, 512 bins)
-→ FFT_Capture (frame control)
-→ FIFO Serializer (4 FIFOs → 1 stream)
-→ AXI4-Stream (uint64)
-→ DMA (S2MM)
-→ PS Memory
-→ Processor Algorithm (frame-based)
+ADC → Channelizer (PFB, 512 bins)  
+→ FFT_Capture (frame control)  
+→ FIFO Serializer (4 FIFOs → 1 stream)  
+→ AXI4-Stream (uint64)  
+→ DMA (S2MM)  
+→ PS Memory  
+→ Processor Algorithm  
 
 ---
 
 ## Key Parameters
 
-- ADC Sampling Rate: 4096 MSPS
-- Decimation: 8
-- Effective BW: 512 MHz
-- Channels (FFT size): 512
-- Samples per clock: 4
-- FPGA clock: 128 MHz
-- Frame size (PS): 512 samples
+- ADC Sampling Rate: 4096 MSPS  
+- Decimation: 8  
+- Effective BW: 512 MHz  
+- Channels (FFT size): 512  
+- Samples per clock: 4  
+- FPGA clock: 128 MHz  
+- Frame size (PS): 512 samples  
 
 ---
 
-## DMA (PL → PS)
+## 📚 Documentation
 
-- Data type: uint64
-- Frame size: 512
-- Buffers: 16
-- Memory: PS DDR
+### FPGA (PL)
 
-Each TLAST corresponds to one DMA frame.
+- [Tx Subsystem (Pulse Generator)](docs/pl_tx_subsystem.md)
+- [Rx Subsystem (Channelizer)](docs/pl_rx_subsystem.md)
+
+### Processor (PS)
+
+- [PS Subsystem](docs/ps_subsystem.md)
 
 ---
 
-## Processor (PS)
+## System Flow
 
-- Event-driven execution (triggered by DMA)
-- No task queueing
-- Frames may be dropped if processing is slower than input rate
+Tx → Rx → PS
 
----
-
-## Data Path in PS
-
-- Stream Read → uint64[512]
-- Bit extraction → real/imag
-- Conversion → complex vector
-- Processing → RMS + peak detection
-
----
-
-## Performance Notes
-
-- Bottleneck: unpacking + type conversion
-- PS cannot keep up with full-rate stream
-- Frames are skipped under load
-
----
-
-## FrFT Integration Plan
-
-- Replace Processor Algorithm with FrFT
-- Keep all other components unchanged
-- Input: complex single [512x1]
-- Accept dropped frames initially
+- Tx generates waveform  
+- Rx captures and channelizes  
+- PS processes frames  
 
 ---