Oganize preload and init functions and parameters (ongoing)

pulsegen_block/soc_resm_init.m

@@ -1,80 +0,0 @@
-%% Rate setup
-fs = 512e6; % Effective fs before interpolation / after decimation
-Ts = 1/fs;
-
-%% Host Sample Time in Simulation
-%TsHost = 5e-5;
-
-SamplesPerCycle = 4;
-
-FPGAClkRate = fs/SamplesPerCycle;
-TsFPGA = 1/FPGAClkRate;
-%% Tx signal generator parameters
-
-% NCO accumulator word length
-NCOAccumWL = 16;
-
-% NCO phase increment scale factor
-NCOIncScale = Ts*2^NCOAccumWL;
-
-% NCO phase increments datatype
-NCOIncDT = numerictype(1,NCOAccumWL,0);
-
-% NCO counter increment datatype
-NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);
-
-%% Test signal parameters
-
-% Pulse width
-pulseWidth = 8.5e-6;
-
-% Pulse start/end frequencies
-pulseCentFreq = 125e6;
-pulseBw = 50e6; % Pulse bandwidth
-
-% Number of pulses
-numPulses = 4;
-
-% Pulse repetition interval
-PRF = 20e3;
-PRI = 1/PRF;
-
-% Output gain
-pulseGenGain = 1;
-
-%% Software parameters
-
-% Signal generator update rate
-TsSW = 0.0025;
-
-%% Simulation parameters
-
-% Sim run time
-stoptime = 10*TsSW;
-
-%% Channelizer parameters
-
-% Number of channels, maximally decimated channelizer M/D=1
-%nChan = 512;
-
-% Taps per band
-%nTapsPerBand = 16;
-
-% Create channelizer object
-%channelizer = dsp.Channelizer('NumFrequencyBands',nChan,...
-%                              'DecimationFactor',nChan,...
-%                              'NumTapsPerBand',nTapsPerBand);
-% Channelizer coefficients
-%channelizerCoeffs = channelizer.coeffs.Numerator;
-
-% Channel bandwidth
-%chanBW = fs/nChan;
-
-% Starting frequency for each channel
-%chanFStart = chanBW/2:chanBW:(fs/2-chanBW/2);
-
-% Number of frames out of channelzier
-%nFrames = nChan/SamplesPerCycle;
-
-% Frame size after serializing x2
-%frameSize = SamplesPerCycle/2;

resources/project/Abllu374wtDd3IliE-5ZoGpf8mM/O_Wj2lFHsFw-dAu1iDbjtB-rERUp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="aux" type="File"/>

resources/project/Abllu374wtDd3IliE-5ZoGpf8mM/TelF4YKeHIop9sma5ly27aHFycIp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="soc_rfsoc_prj_startup.m" type="File"/>

resources/project/Abllu374wtDd3IliE-5ZoGpf8mM/a4IuKwbTrz65HsB1qy2BUvphPvUp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="soc_rfsoc_preload.m" type="File"/>

resources/project/Abllu374wtDd3IliE-5ZoGpf8mM/ep2eC_pbgpB45JNIfZ_kN-IOldEp.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="soc_rfsoc_startup.m" type="File"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/aIKCkzvF2b1sr3-2vSSYXiPFCBcd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info Ref="utilities/aux" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/aIKCkzvF2b1sr3-2vSSYXiPFCBcp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="ac65d1bc-e8fa-4056-83e4-eaba335b5aa3" type="Reference"/>

resources/project/HoHDHQ_WvHAAKj5aJOrvrg_vpt8/xXlmKuOQ7YT_G1elNhbKQIUqSRMd.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Info description=""/>
+<Info description="RFSoC Channelizer + PS Processing (R-ESM Prototype)&#10;&#10;This project is based on the RFSoC SoC Blockset reference design, adapted as a prototype for a Radar Electronic Support Measures (R-ESM) receiver.&#10;&#10;The system implements a high-throughput signal chain in the FPGA (PL) and performs frame-based processing in the processor (PS)."/>

resources/project/KAXfQgCar2Yb8zOxgvf9hdmLP1E/Fd9H20iNQ049h3heONYKHGeEV4Ud.xml

@@ -1,4 +1,4 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Info File="utilities/soc_rfsoc_startup.m" GroupUUID="default" Icon="" Name="soc_rfsoc_startup" Type="StartUp" Visible="0">
+<Info File="utilities/soc_rfsoc_prj_startup.m" GroupUUID="default" Icon="" Name="soc_rfsoc_startup" Type="StartUp" Visible="0">
     <Extension Name="StartUpPrev" Value="HEAD"/>
 </Info>

resources/project/MEnu9bsvaE1ht88eLRvHOJK-Wu0/o2mWUvp8wHgCXFtZfz-nw7fAWpYp.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="soc_resm_init.asv" type="File"/>

resources/project/MEnu9bsvaE1ht88eLRvHOJK-Wu0/ztPtmXD5xpkIGcNCb-BxiWJmzLUp.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="soc_resm_init.m" type="File"/>

resources/project/O_Wj2lFHsFw-dAu1iDbjtB-rERU/lDMgbB2qVwwu-5ETYbC5dxpFwTId.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/O_Wj2lFHsFw-dAu1iDbjtB-rERU/lDMgbB2qVwwu-5ETYbC5dxpFwTIp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="1" type="DIR_SIGNIFIER"/>

utilities/soc_rfsoc_init.m

@@ -1,22 +1,108 @@
-function soc_rfsoc_init(mdlPath)
+%%  Derived from preload
-% Initialization fcn for the model. It sets the model-wide params
-% which are derived based on sample rate.
 
-% 'FrameSize and 'NumBuffers' variables are set during model
+fs_eff = fs_RF/IntDecFactor; % Effective fs before interpolation / after decimation
-% PreLoadFcn callback into base workspace. These two variables should be
+Ts_eff = 1/fs_eff;
-% changed directly at the MATLAB command
 
-% FrameSize = evalin('base','FrameSize');
+%% Host Sample Time in Simulation
+%TsHost = 5e-5;
 
-dacSampleRate = get_param([mdlPath '/RF Data Converter'], 'dacSampleRate');
+FPGAClkRate = fs_eff/SamplesPerCycle;
-dacSampleRate = evalin('base', dacSampleRate)*1e6;
+TsFPGA = 1/FPGAClkRate;
-dacSamplesPerCycle = str2double(get_param([mdlPath '/RF Data Converter'], 'dacSamplesPerCycle'));
+%% Tx signal generator parameters
-dacInterpolationMode = str2double(get_param([mdlPath '/RF Data Converter'], 'interpolationMode'));
-streamClkFrequency = dacSampleRate/(dacSamplesPerCycle*dacInterpolationMode);
 
-SampleTime = 1/streamClkFrequency;
+% NCO accumulator word length
+NCOAccumWL = 16;
+
+% NCO phase increment scale factor
+NCOIncScale = Ts_eff*2^NCOAccumWL;
+
+% NCO phase increments datatype
+NCOIncDT = numerictype(1,NCOAccumWL,0);
+
+% NCO counter increment datatype
+NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);
+
+%% Test signal parameters
+
+% Pulse width
+pulseWidth = 8.5e-6;
+
+% Pulse start/end frequencies
+pulseCentFreq = 125e6;
+pulseBw = 50e6; % Pulse bandwidth
+
+% Number of pulses
+numPulses = 4;
+
+% Pulse repetition interval
+PRF = 20e3;
+PRI = 1/PRF;
+
+% Output gain
+pulseGenGain = 1;
+
+%% Software parameters
+
+% Signal generator update rate
+TsSW = 0.0025;
+
+%% Simulation parameters
+
+% Sim run time
+stoptime = 10*TsSW;
+
+%% Channelizer parameters
+
+% Number of channels, maximally decimated channelizer M/D=1
+%nChan = 512;
+
+% Taps per band
+%nTapsPerBand = 16;
+
+% Create channelizer object
+%channelizer = dsp.Channelizer('NumFrequencyBands',nChan,...
+%                              'DecimationFactor',nChan,...
+%                              'NumTapsPerBand',nTapsPerBand);
+% Channelizer coefficients
+%channelizerCoeffs = channelizer.coeffs.Numerator;
+
+% Channel bandwidth
+%chanBW = fs/nChan;
+
+% Starting frequency for each channel
+%chanFStart = chanBW/2:chanBW:(fs/2-chanBW/2);
+
+% Number of frames out of channelzier
+%nFrames = nChan/SamplesPerCycle;
+
+% Frame size after serializing x2
+%frameSize = SamplesPerCycle/2;
 
 
-% derived model-wide variables set into base workspace.
+
-assignin('base','SampleTime', SampleTime);
+
-end
+
+% function soc_rfsoc_init(mdlPath)
+% % Initialization fcn for the model. It sets the model-wide params
+% % which are derived based on sample rate.
+% 
+% % 'FrameSize and 'NumBuffers' variables are set during model
+% % PreLoadFcn callback into base workspace. These two variables should be
+% % changed directly at the MATLAB command
+% 
+% % FrameSize = evalin('base','FrameSize');
+% 
+% dacSampleRate = get_param([mdlPath '/RF Data Converter'], 'dacSampleRate');
+% dacSampleRate = evalin('base', dacSampleRate)*1e6;
+% dacSamplesPerCycle = str2double(get_param([mdlPath '/RF Data Converter'], 'dacSamplesPerCycle'));
+% dacInterpolationMode = str2double(get_param([mdlPath '/RF Data Converter'], 'interpolationMode'));
+% streamClkFrequency = dacSampleRate/(dacSamplesPerCycle*dacInterpolationMode);
+% 
+% SampleTime = 1/streamClkFrequency;
+% 
+% % derived model-wide variables set into base workspace.
+% assignin('base','FPGAClkRate', streamClkFrequency);
+% assignin('base','TsFPGA', SampleTime);
+% assignin('base','SamplesPerCycle', dacSamplesPerCycle);
+% assignin('base','IntDecFactor', dacInterpolationMode);
+% end

utilities/soc_rfsoc_preload.m

@@ -0,0 +1,12 @@
+%% DMA and SW parameters
+FrameSize = 512;
+NumBuffers = 16;
+%downSamplingFactor = 64;
+%SrcSel = 0;
+
+%% Rate setup (use txspectrum and rxspectrum tools)
+
+% local
+fs_RF = 4096e6; % RF data converter sampling rate
+fs_RF_MSPS = fs_RF/1e6; % Parameter on block is in Mega samples/s
+RFDC_NCOFreq_GHz = 0.768; % RFDC's NCO frequency in Giga Hertz

utilities/soc_rfsoc_prj_startup.m

@@ -3,4 +3,6 @@
 % Configure HDL Coder to use Xilinx Vivado for HDL workflows.
 %
 hdlsetuptoolpath('ToolName','Xilinx Vivado', ...
-                 'ToolPath','/tools/Xilinx/Vivado/2024.1/bin/vivado');
+                 'ToolPath','/tools/Xilinx/Vivado/2024.1/bin/vivado');
+
+%%