Oganize preload and init functions and parameters (ongoing)
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canisio
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%% Rate setup
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fs = 512e6; % Effective fs before interpolation / after decimation
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Ts = 1/fs;
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%% Host Sample Time in Simulation
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%TsHost = 5e-5;
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SamplesPerCycle = 4;
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FPGAClkRate = fs/SamplesPerCycle;
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TsFPGA = 1/FPGAClkRate;
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%% Tx signal generator parameters
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% NCO accumulator word length
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NCOAccumWL = 16;
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% NCO phase increment scale factor
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NCOIncScale = Ts*2^NCOAccumWL;
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% NCO phase increments datatype
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NCOIncDT = numerictype(1,NCOAccumWL,0);
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% NCO counter increment datatype
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NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);
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%% Test signal parameters
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% Pulse width
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pulseWidth = 8.5e-6;
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% Pulse start/end frequencies
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pulseCentFreq = 125e6;
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pulseBw = 50e6; % Pulse bandwidth
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% Number of pulses
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numPulses = 4;
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% Pulse repetition interval
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PRF = 20e3;
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PRI = 1/PRF;
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% Output gain
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pulseGenGain = 1;
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%% Software parameters
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% Signal generator update rate
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TsSW = 0.0025;
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%% Simulation parameters
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% Sim run time
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stoptime = 10*TsSW;
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%% Channelizer parameters
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% Number of channels, maximally decimated channelizer M/D=1
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%nChan = 512;
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% Taps per band
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%nTapsPerBand = 16;
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% Create channelizer object
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%channelizer = dsp.Channelizer('NumFrequencyBands',nChan,...
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% 'DecimationFactor',nChan,...
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% 'NumTapsPerBand',nTapsPerBand);
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% Channelizer coefficients
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%channelizerCoeffs = channelizer.coeffs.Numerator;
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% Channel bandwidth
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%chanBW = fs/nChan;
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% Starting frequency for each channel
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%chanFStart = chanBW/2:chanBW:(fs/2-chanBW/2);
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% Number of frames out of channelzier
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%nFrames = nChan/SamplesPerCycle;
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% Frame size after serializing x2
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%frameSize = SamplesPerCycle/2;
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<?xml version="1.0" encoding="UTF-8"?>
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<Info location="aux" type="File"/>
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<?xml version="1.0" encoding="UTF-8"?>
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<Info location="soc_rfsoc_prj_startup.m" type="File"/>
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<?xml version="1.0" encoding="UTF-8"?>
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<Info location="soc_rfsoc_preload.m" type="File"/>
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<?xml version="1.0" encoding="UTF-8"?>
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<Info location="soc_rfsoc_startup.m" type="File"/>
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<?xml version="1.0" encoding="UTF-8"?>
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<Info Ref="utilities/aux" Type="Relative"/>
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<?xml version="1.0" encoding="UTF-8"?>
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<Info location="ac65d1bc-e8fa-4056-83e4-eaba335b5aa3" type="Reference"/>
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<?xml version="1.0" encoding="UTF-8"?>
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<Info description=""/>
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<Info description="RFSoC Channelizer + PS Processing (R-ESM Prototype) This project is based on the RFSoC SoC Blockset reference design, adapted as a prototype for a Radar Electronic Support Measures (R-ESM) receiver. The system implements a high-throughput signal chain in the FPGA (PL) and performs frame-based processing in the processor (PS)."/>
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<?xml version="1.0" encoding="UTF-8"?>
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<Info File="utilities/soc_rfsoc_startup.m" GroupUUID="default" Icon="" Name="soc_rfsoc_startup" Type="StartUp" Visible="0">
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<Info File="utilities/soc_rfsoc_prj_startup.m" GroupUUID="default" Icon="" Name="soc_rfsoc_startup" Type="StartUp" Visible="0">
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<Extension Name="StartUpPrev" Value="HEAD"/>
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</Info>
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<?xml version="1.0" encoding="UTF-8"?>
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<Info location="soc_resm_init.asv" type="File"/>
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<?xml version="1.0" encoding="UTF-8"?>
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<Info location="soc_resm_init.m" type="File"/>
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<?xml version="1.0" encoding="UTF-8"?>
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<Info/>
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<?xml version="1.0" encoding="UTF-8"?>
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<Info location="1" type="DIR_SIGNIFIER"/>
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function soc_rfsoc_init(mdlPath)
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% Initialization fcn for the model. It sets the model-wide params
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% which are derived based on sample rate.
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%% Derived from preload
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% 'FrameSize and 'NumBuffers' variables are set during model
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% PreLoadFcn callback into base workspace. These two variables should be
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% changed directly at the MATLAB command
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fs_eff = fs_RF/IntDecFactor; % Effective fs before interpolation / after decimation
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Ts_eff = 1/fs_eff;
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% FrameSize = evalin('base','FrameSize');
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%% Host Sample Time in Simulation
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%TsHost = 5e-5;
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dacSampleRate = get_param([mdlPath '/RF Data Converter'], 'dacSampleRate');
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dacSampleRate = evalin('base', dacSampleRate)*1e6;
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dacSamplesPerCycle = str2double(get_param([mdlPath '/RF Data Converter'], 'dacSamplesPerCycle'));
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dacInterpolationMode = str2double(get_param([mdlPath '/RF Data Converter'], 'interpolationMode'));
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streamClkFrequency = dacSampleRate/(dacSamplesPerCycle*dacInterpolationMode);
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FPGAClkRate = fs_eff/SamplesPerCycle;
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TsFPGA = 1/FPGAClkRate;
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%% Tx signal generator parameters
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SampleTime = 1/streamClkFrequency;
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% NCO accumulator word length
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NCOAccumWL = 16;
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% NCO phase increment scale factor
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NCOIncScale = Ts_eff*2^NCOAccumWL;
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% NCO phase increments datatype
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NCOIncDT = numerictype(1,NCOAccumWL,0);
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% NCO counter increment datatype
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NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);
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%% Test signal parameters
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% Pulse width
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pulseWidth = 8.5e-6;
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% Pulse start/end frequencies
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pulseCentFreq = 125e6;
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pulseBw = 50e6; % Pulse bandwidth
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% Number of pulses
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numPulses = 4;
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% Pulse repetition interval
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PRF = 20e3;
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PRI = 1/PRF;
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% Output gain
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pulseGenGain = 1;
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%% Software parameters
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% Signal generator update rate
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TsSW = 0.0025;
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%% Simulation parameters
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% Sim run time
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stoptime = 10*TsSW;
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%% Channelizer parameters
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% Number of channels, maximally decimated channelizer M/D=1
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%nChan = 512;
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% Taps per band
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%nTapsPerBand = 16;
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% Create channelizer object
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%channelizer = dsp.Channelizer('NumFrequencyBands',nChan,...
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% 'DecimationFactor',nChan,...
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% 'NumTapsPerBand',nTapsPerBand);
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% Channelizer coefficients
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%channelizerCoeffs = channelizer.coeffs.Numerator;
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% Channel bandwidth
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%chanBW = fs/nChan;
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% Starting frequency for each channel
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%chanFStart = chanBW/2:chanBW:(fs/2-chanBW/2);
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% Number of frames out of channelzier
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%nFrames = nChan/SamplesPerCycle;
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% Frame size after serializing x2
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%frameSize = SamplesPerCycle/2;
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% derived model-wide variables set into base workspace.
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assignin('base','SampleTime', SampleTime);
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end
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% function soc_rfsoc_init(mdlPath)
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% % Initialization fcn for the model. It sets the model-wide params
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% % which are derived based on sample rate.
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%
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% % 'FrameSize and 'NumBuffers' variables are set during model
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% % PreLoadFcn callback into base workspace. These two variables should be
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% % changed directly at the MATLAB command
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%
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% % FrameSize = evalin('base','FrameSize');
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%
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% dacSampleRate = get_param([mdlPath '/RF Data Converter'], 'dacSampleRate');
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% dacSampleRate = evalin('base', dacSampleRate)*1e6;
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% dacSamplesPerCycle = str2double(get_param([mdlPath '/RF Data Converter'], 'dacSamplesPerCycle'));
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% dacInterpolationMode = str2double(get_param([mdlPath '/RF Data Converter'], 'interpolationMode'));
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% streamClkFrequency = dacSampleRate/(dacSamplesPerCycle*dacInterpolationMode);
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%
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% SampleTime = 1/streamClkFrequency;
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%
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% % derived model-wide variables set into base workspace.
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% assignin('base','FPGAClkRate', streamClkFrequency);
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% assignin('base','TsFPGA', SampleTime);
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% assignin('base','SamplesPerCycle', dacSamplesPerCycle);
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% assignin('base','IntDecFactor', dacInterpolationMode);
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% end
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12
utilities/soc_rfsoc_preload.m
Normal file
12
utilities/soc_rfsoc_preload.m
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%% DMA and SW parameters
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FrameSize = 512;
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NumBuffers = 16;
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%downSamplingFactor = 64;
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%SrcSel = 0;
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%% Rate setup (use txspectrum and rxspectrum tools)
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% local
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fs_RF = 4096e6; % RF data converter sampling rate
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fs_RF_MSPS = fs_RF/1e6; % Parameter on block is in Mega samples/s
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RFDC_NCOFreq_GHz = 0.768; % RFDC's NCO frequency in Giga Hertz
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% Configure HDL Coder to use Xilinx Vivado for HDL workflows.
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%
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hdlsetuptoolpath('ToolName','Xilinx Vivado', ...
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'ToolPath','/tools/Xilinx/Vivado/2024.1/bin/vivado');
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'ToolPath','/tools/Xilinx/Vivado/2024.1/bin/vivado');
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%%
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