3 Commits

Author SHA1 Message Date
canisio
65cef793ac Removed RMS and Fmax outputs
Formatted top diagrams
2026-04-29 11:30:02 -03:00
canisio
99c6b62fc6 Added CwMode as toggle switch 2026-04-29 10:44:14 -03:00
canisio
dc76c69731 added folder "codegen_frft" to the project (it was renamed) 2026-04-29 10:21:17 -03:00
15 changed files with 34 additions and 10 deletions

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<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft/codegen/mex/fracF_cg/interface" Type="Relative"/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft/codegen/mex/fracF_cg" Type="Relative"/>

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@@ -39,23 +39,27 @@ PRI = 1/PRF;
pulseT = 10e-6; pulseT = 10e-6;
% CW mode (bypass pulse generation) % CW mode (bypass pulse generation)
CwMode = false; %CwMode = false;
% Counter mode (bypass pulse and CW generation) % Counter mode (bypass pulse and CW generation)
CounterMode = true; %CounterMode = true;
% Output gain % Output gain
pulseGenGain = 1; pulseGenGain = 1;
%% Software parameters %% Simulation/External Mode parameters (conditional)
bd = bdroot; % Retrive which model is calling this function
% Signal generator update rate switch bd
case 'soc_rfsoc_top'
TsSW = 0.0005; % Signal generator and capture update rate
StopTime = 0.0025; % Simulation total time
case 'gm_soc_rfsoc_top_sw'
TsSW = 0.5; TsSW = 0.5;
StopTime = 10;
%% Simulation parameters otherwise
error('rfsoc_init: InvalidModel (%s not supported).', bd);
% Sim run time end
%stoptime = TsFPGA*(9 + 1*348 + 1 + 2*128 + 1); %10*TsSW; %TsFPGA*(1*128+348)
%% Channelizer parameters %% Channelizer parameters