8 Commits

Author SHA1 Message Date
canisio
19fd4dfb2d second validation of MeanPowSpec before branch to FrFT. Created slides on interface and tested several combinations of paramters. Resulds within expected. 2026-04-30 12:24:24 -03:00
canisio
1622f922f9 MeanPowSpec validated on board 2026-04-29 17:07:10 -03:00
canisio
041218aa7f test MeanPowSpec on ZCU111 2026-04-29 16:35:55 -03:00
canisio
d9f7798814 Added Mean Power Spectrum calculation on PS 2026-04-29 16:10:21 -03:00
canisio
1ab873419e clean version after tagging 2026-04-29 14:11:51 -03:00
canisio
65cef793ac Removed RMS and Fmax outputs
Formatted top diagrams
2026-04-29 11:30:02 -03:00
canisio
99c6b62fc6 Added CwMode as toggle switch 2026-04-29 10:44:14 -03:00
canisio
dc76c69731 added folder "codegen_frft" to the project (it was renamed) 2026-04-29 10:21:17 -03:00
17 changed files with 48 additions and 23 deletions

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<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft/codegen/mex/fracF_cg/interface" Type="Relative"/>

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<Info Ref="codegen_frft/codegen" Type="Relative"/>

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<Info Ref="codegen_frft/codegen/mex" Type="Relative"/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft/codegen/mex/fracF_cg" Type="Relative"/>

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@@ -25,7 +25,7 @@ NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);
% Pulse start/end frequencies
pulseCentFreq = 0e6;
pulseBw = 50e6; % Pulse bandwidth
pulseBw = 40e6; % Pulse bandwidth
% Number of pulses
numPulses = 10;
@@ -34,28 +34,33 @@ numPulses = 10;
PRF = 7.5e3;
PRI = 1/PRF;
% Pulse time duration
%pulseT = 10; % use very long pulse help emulate CW
pulseT = 10e-6;
pulseT = 20e-6;
% CW mode (bypass pulse generation)
CwMode = false;
%CwMode = false;
% Counter mode (bypass pulse and CW generation)
CounterMode = true;
%CounterMode = true;
% Output gain
pulseGenGain = 1;
%% Software parameters
%% Simulation/External Mode parameters (conditional)
bd = bdroot; % Retrive which model is calling this function
% Signal generator update rate
TsSW = 0.5;
%% Simulation parameters
% Sim run time
%stoptime = TsFPGA*(9 + 1*348 + 1 + 2*128 + 1); %10*TsSW; %TsFPGA*(1*128+348)
switch bd
case 'soc_rfsoc_top'
TsSW = 0.0005; % Signal generator and capture update rate
StopTime = 0.025; % Simulation total time
case 'gm_soc_rfsoc_top_sw'
TsSW = 0.25;
StopTime = 250;
otherwise
error('rfsoc_init: InvalidModel (%s not supported).', bd);
end
%% Channelizer parameters