Stable single frame (512 samples) baseline before capture redesign

tested remotely. OK

README.md

@@ -4,81 +4,63 @@
 
 This project is based on the RFSoC SoC Blockset reference design, adapted as a prototype for a Radar Electronic Support Measures (R-ESM) receiver.
 
-### Current Status
+The system implements a high-throughput signal chain in the FPGA (PL) and performs frame-based processing in the processor (PS).
 
-- Tx subsystem: simple tone generator (to be replaced by LFM pulse generator)
+---
+
+## Current Status
+
+- Tx subsystem: LFM pulse generator (DDS-based, complex output)
 - Rx subsystem: fully functional channelizer pipeline (PFB-based)
-- PL → PS interface: AXI4-Stream + DMA working
+- PL → PS interface: AXI4-Stream + DMA operational
 - PS processing: frame-based algorithm (RMS + peak detection)
 
 ---
 
 ## System Architecture
 
-ADC → Channelizer (PFB, 512 bins)
+ADC → Channelizer (PFB, 512 bins)  
-→ FFT_Capture (frame control)
+→ FFT_Capture (frame control)  
-→ FIFO Serializer (4 FIFOs → 1 stream)
+→ FIFO Serializer (4 FIFOs → 1 stream)  
-→ AXI4-Stream (uint64)
+→ AXI4-Stream (uint64)  
-→ DMA (S2MM)
+→ DMA (S2MM)  
-→ PS Memory
+→ PS Memory  
-→ Processor Algorithm (frame-based)
+→ Processor Algorithm  
 
 ---
 
 ## Key Parameters
 
-- ADC Sampling Rate: 4096 MSPS
+- ADC Sampling Rate: 4096 MSPS  
-- Decimation: 8
+- Decimation: 8  
-- Effective BW: 512 MHz
+- Effective BW: 512 MHz  
-- Channels (FFT size): 512
+- Channels (FFT size): 512  
-- Samples per clock: 4
+- Samples per clock: 4  
-- FPGA clock: 128 MHz
+- FPGA clock: 128 MHz  
-- Frame size (PS): 512 samples
+- Frame size (PS): 512 samples  
 
 ---
 
-## DMA (PL → PS)
+## 📚 Documentation
 
-- Data type: uint64
+### FPGA (PL)
-- Frame size: 512
-- Buffers: 16
-- Memory: PS DDR
 
-Each TLAST corresponds to one DMA frame.
+- [Tx Subsystem (Pulse Generator)](docs/pl_tx_subsystem.md)
+- [Rx Subsystem (Channelizer)](docs/pl_rx_subsystem.md)
+
+### Processor (PS)
+
+- [PS Subsystem](docs/ps_subsystem.md)
 
 ---
 
-## Processor (PS)
+## System Flow
 
-- Event-driven execution (triggered by DMA)
+Tx → Rx → PS
-- No task queueing
-- Frames may be dropped if processing is slower than input rate
 
----
+- Tx generates waveform  
-
+- Rx captures and channelizes  
-## Data Path in PS
+- PS processes frames  
-
-- Stream Read → uint64[512]
-- Bit extraction → real/imag
-- Conversion → complex vector
-- Processing → RMS + peak detection
-
----
-
-## Performance Notes
-
-- Bottleneck: unpacking + type conversion
-- PS cannot keep up with full-rate stream
-- Frames are skipped under load
-
----
-
-## FrFT Integration Plan
-
-- Replace Processor Algorithm with FrFT
-- Keep all other components unchanged
-- Input: complex single [512x1]
-- Accept dropped frames initially
 
 ---
 

docs/pl_rx_subsystem.md

@@ -0,0 +1,134 @@
+# 📡 PL Rx Subsystem (Channelizer)
+
+[🏠 Project Home](../README.md)
+
+---
+
+## Overview
+
+The Rx subsystem implements a **polyphase filter bank (PFB) channelizer** followed by FFT processing.
+
+It converts wideband ADC input into frequency-domain channels and streams the result to the PS.
+
+A **bypass path** is also available for raw data inspection and debugging.
+
+---
+
+## Architecture
+
+### Channelizer Path (default)
+
+ADC
+ ↓
+PFB Channelizer (Decimation + Filtering)
+ ↓
+FFT (512 bins)
+ ↓
+FFT Capture
+ ↓
+FIFO Serializer (4 → 1)
+ ↓
+AXI4-Stream
+ ↓
+DMA
+
+---
+
+### Bypass Path (Debug / Raw Data)
+
+ADC
+ ↓
+Bypass Path
+ ↓
+FIFO / Serializer
+ ↓
+AXI4-Stream
+ ↓
+DMA
+
+---
+
+## Bypass Functionality
+
+The bypass allows direct observation of the input signal without channelization.
+
+### Purpose
+
+- Debugging and validation
+- Access to raw ADC-domain data
+- Comparison with channelized output
+- Verification of downstream processing
+
+---
+
+### Behavior
+
+- Input data is routed directly to output
+- No filtering or FFT applied
+- Maintains same output interface (AXI4-Stream)
+
+---
+
+### Selection Mechanism
+
+A selector signal chooses between:
+
+- Channelizer output (normal operation)
+- Bypass output (raw data)
+
+Implementation typically uses:
+- Parallel paths
+- Output switching logic
+
+---
+
+## Processing Chain (Channelizer Mode)
+
+### ADC Input
+- Sampling rate: 4096 MSPS
+
+### PFB Channelizer
+- Decimation: 8
+- Effective bandwidth: 512 MHz
+
+### FFT
+- Size: 512
+- Produces frequency bins
+
+### FFT Capture
+- Controls frame boundaries
+
+### FIFO Serializer
+- Converts parallel streams into single stream
+
+---
+
+## AXI4-Stream Output
+
+- Data type: uint64
+- Packed real/imag
+- TLAST = frame boundary
+
+---
+
+## Data Format
+
+- Frame size: 512 samples
+- Complex values packed into uint64
+
+---
+
+## Key Characteristics
+
+- Fully streaming pipeline
+- High throughput
+- Deterministic latency
+- Supports dual-mode operation (channelizer / bypass)
+
+---
+
+## 🔗 Related Components
+
+- [🏠 Project Home](../README.md)
+- [PL Tx Subsystem](pl_tx_subsystem.md)
+- [PS Subsystem](ps_subsystem.md)

docs/pl_tx_subsystem.md

@@ -0,0 +1,177 @@
+# 📡 PL Tx Subsystem (Pulse & Continuous LFM Generator)
+
+[🏠 Project Home](../README.md)
+
+---
+
+## Overview
+
+The Tx subsystem implements a **pulse-based and continuous Linear Frequency Modulated (LFM) chirp generator** using a DDS/NCO architecture in the FPGA (PL).
+
+The generator produces **complex baseband output**:
+
+x[n] = exp(j·φ[n])
+
+and operates deterministically in the PL after a trigger from the PS.
+
+---
+
+## Architecture
+
+TxPulseStart (PS)
+        ↓
+pulse_gen_ctrl (FSM)
+        ↓
+   tx_active
+        ↓
+Phase Increment Logic
+        ↓
+      NCO (DDS)
+        ↓
+   Complex Output (I/Q)
+
+---
+
+## Operating Modes
+
+The subsystem now supports multiple Tx modes:
+
+### 1. Pulsed LFM (default)
+
+- Chirp generated only during pulse window
+- Phase resets at each pulse start
+- Standard radar burst operation
+
+---
+
+### 2. CW Mode (Continuous Wave)
+
+- `tx_active = 1` continuously
+- Generates a single-tone output
+- Achieved by setting constant phase increment
+
+---
+
+### 3. Continuous LFM (Workaround Implementation)
+
+- `tx_active` forced HIGH continuously  
+- A **1-cycle LOW pulse** is inserted periodically  
+- This LOW→HIGH transition **resets the NCO**
+
+Result:
+- Continuous chirp
+- Bounded bandwidth
+- Periodic repetition of LFM
+
+---
+
+## Chirp Generation Principle
+
+The chirp is generated using a second-order phase accumulator:
+
+Δφ[n] = Δφ[n−1] + step  
+φ[n]  = φ[n−1] + Δφ[n]
+
+This results in a linear frequency sweep.
+
+---
+
+## Parameterization (PS → PL)
+
+Inputs:
+
+- Center frequency: Fc  
+- Bandwidth: B  
+- Pulse width: N (samples)
+
+Derived internally:
+
+f_start = Fc − B/2  
+step    = B / (N − 1)
+
+These values are converted to DDS phase increments before being written to PL registers.
+
+---
+
+## Pulse Timing (FSM)
+
+States:
+
+- IDLE: waits for trigger and latches parameters  
+- ACTIVE: generates pulses  
+- DONE: waits for trigger reset  
+
+---
+
+## Timing Behavior
+
+### Pulsed Mode
+
+|<------ PRI ------>|
+|<-- pulse -->| idle |
+
+- tx_active = 1 → chirp output  
+- tx_active = 0 → output zero  
+
+---
+
+### Continuous LFM Mode
+
+tx_active behavior:
+
+1 1 1 1 1 0 1 1 1 1 ...
+
+- 1-cycle LOW inserted at end of chirp period  
+- Rising edge resets NCO  
+- Defines chirp repetition interval  
+
+---
+
+## CW / Continuous LFM Implementation Details
+
+- CW mode bypasses FSM output
+- A dedicated counter generates periodic reset pulses
+- Reset timing is based on `pulse_width_cycles`
+
+Important:
+
+- Reset pulse is exactly **1 clock cycle**
+- Ensures deterministic NCO restart
+- Decoupled from PRI/FSM timing
+
+---
+
+## Burst Trigger (PS Interaction)
+
+- Controlled via TxPulseStart (memory-mapped register)
+- Rising edge triggers burst
+- PL runs autonomously afterward
+
+---
+
+## Key Characteristics
+
+- Deterministic timing (128 MHz)
+- Efficient DDS (adder-based)
+- Complex output (I/Q)
+- Supports:
+  - Pulsed radar mode
+  - Continuous wave (CW)
+  - Continuous LFM (periodic chirp)
+
+---
+
+## Design Notes
+
+- FSM controls **timing (when to transmit)**
+- NCO controls **frequency evolution**
+- Continuous LFM implemented via **tx_active edge reuse**
+- Minimal hardware overhead (no additional NCO logic)
+
+---
+
+## 🔗 Related Components
+
+- [🏠 Project Home](../README.md)
+- [PL Rx Subsystem](pl_rx_subsystem.md)
+- [PS Subsystem](ps_subsystem.md)

docs/ps_subsystem.md

@@ -0,0 +1,85 @@
+# 🧠 PS Subsystem (Control + Processing)
+
+[🏠 Project Home](../README.md)
+
+---
+
+## Overview
+
+The PS subsystem is responsible for:
+
+- Configuring PL subsystems
+- Receiving data via DMA
+- Performing frame-based processing
+
+---
+
+## Responsibilities
+
+### Control
+
+- Writes parameters to PL registers:
+  - Tx generator configuration
+- Generates TxPulseStart trigger
+
+---
+
+### DMA Handling
+
+- AXI4-Stream → DMA (S2MM)
+- Data stored in PS DDR
+
+Configuration:
+- Frame size: 512
+- Buffers: 16
+
+---
+
+### Processing Pipeline
+
+DMA → uint64[512]  
+→ unpack real/imag  
+→ convert to complex  
+→ RMS + peak detection  
+
+---
+
+## Execution Model
+
+- Event-driven (DMA trigger)
+- No buffering queue
+- Frames may be dropped
+
+---
+
+## Performance Notes
+
+- Bottleneck: unpacking + conversion
+- Cannot sustain full-rate input
+
+---
+
+## Interaction with PL
+
+### Tx Control
+- Low-rate trigger (~Hz)
+- Starts burst generation
+
+### Rx Data
+- Continuous high-rate stream
+
+---
+
+## Future Work
+
+- Replace processing with FrFT
+- NEON optimization
+- Throughput improvements
+
+---
+
+## 🔗 Related Components
+
+- [🏠 Project Home](../README.md)
+- [PL Tx Subsystem](pl_tx_subsystem.md)
+- [PL Rx Subsystem](pl_rx_subsystem.md)

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+<Info location="ps_subsystem.md" type="File"/>

resources/project/rW25SbP5jRWeIzL7_iMpZrrygYk/XVu9f1ZjVk2AJ99l5f9CAU_dcMEd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/rW25SbP5jRWeIzL7_iMpZrrygYk/XVu9f1ZjVk2AJ99l5f9CAU_dcMEp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="pl_rx_subsystem.md" type="File"/>

resources/project/rW25SbP5jRWeIzL7_iMpZrrygYk/mT-GHnZui1JHuHyjd1ddvO5o-Tsd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/rW25SbP5jRWeIzL7_iMpZrrygYk/mT-GHnZui1JHuHyjd1ddvO5o-Tsp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="1" type="DIR_SIGNIFIER"/>

resources/project/rW25SbP5jRWeIzL7_iMpZrrygYk/uS1pkYbM9dJDnKGtwfzZHrJKyTYd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/rW25SbP5jRWeIzL7_iMpZrrygYk/uS1pkYbM9dJDnKGtwfzZHrJKyTYp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="pl_tx_subsystem.md" type="File"/>

utilities/soc_rfsoc_init.m

@@ -1,22 +1,81 @@
-function soc_rfsoc_init(mdlPath)
+%%  Derived from preload
-% Initialization fcn for the model. It sets the model-wide params
+fs_eff = fs_RF/IntDecFactor; % Effective fs before interpolation / after decimation
-% which are derived based on sample rate.
+Ts_eff = 1/fs_eff;
 
-% 'FrameSize and 'NumBuffers' variables are set during model
+%% Host Sample Time in Simulation
-% PreLoadFcn callback into base workspace. These two variables should be
+%TsHost = 5e-5;
-% changed directly at the MATLAB command
 
-% FrameSize = evalin('base','FrameSize');
+FPGAClkRate = fs_eff/SamplesPerCycle;
+TsFPGA = 1/FPGAClkRate;
+%% Tx signal generator parameters
 
-dacSampleRate = get_param([mdlPath '/RF Data Converter'], 'dacSampleRate');
+% NCO accumulator word length
-dacSampleRate = evalin('base', dacSampleRate)*1e6;
+NCOAccumWL = 16;
-dacSamplesPerCycle = str2double(get_param([mdlPath '/RF Data Converter'], 'dacSamplesPerCycle'));
-dacInterpolationMode = str2double(get_param([mdlPath '/RF Data Converter'], 'interpolationMode'));
-streamClkFrequency = dacSampleRate/(dacSamplesPerCycle*dacInterpolationMode);
 
-SampleTime = 1/streamClkFrequency;
+% NCO phase increment scale factor
+NCOIncScale = Ts_eff*2^NCOAccumWL;
 
+% NCO phase increments datatype
+NCOIncDT = numerictype(1,NCOAccumWL,0);
 
-% derived model-wide variables set into base workspace.
+% NCO counter increment datatype
-assignin('base','SampleTime', SampleTime);
+NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);
-end
+
+%% Test signal parameters
+
+% Pulse width
+pulseWidth = 4e-6;
+
+% Pulse start/end frequencies
+pulseCentFreq = 100e6;
+pulseBw = 5e6; % Pulse bandwidth
+
+% Number of pulses
+numPulses = 10;
+
+% Pulse repetition interval
+PRF = 20e3;
+PRI = 1/PRF;
+
+% CW mode (bypass pulse generation)
+CwMode = true;
+
+% Output gain
+pulseGenGain = 1;
+
+%% Software parameters
+
+% Signal generator update rate
+TsSW = 0.5e-3;
+
+%% Simulation parameters
+
+% Sim run time
+stoptime = 10*TsSW;
+
+%% Channelizer parameters
+
+%Number of channels, maximally decimated channelizer M/D=1
+nChan = 512;
+
+%Taps per band
+nTapsPerBand = 16;
+
+%Create channelizer object
+channelizer = dsp.Channelizer('NumFrequencyBands',nChan,...
+                             'DecimationFactor',nChan,...
+                             'NumTapsPerBand',nTapsPerBand);
+%Channelizer coefficients
+channelizerCoeffs = channelizer.coeffs.Numerator;
+
+%Channel bandwidth
+%chanBW = fs/nChan;
+
+%Starting frequency for each channel
+%chanFStart = chanBW/2:chanBW:(fs/2-chanBW/2);
+
+%Number of frames out of channelzier
+nFrames = nChan/SamplesPerCycle;
+
+% Frame size after serializing x2
+%frameSize = SamplesPerCycle/2;

utilities/soc_rfsoc_postload.m

@@ -0,0 +1,5 @@
+%% Get parameters configured on the block 
+IntDecFactor = str2double(get_param([bdroot '/RF Data Converter'], ...
+    'interpolationMode')); % Interpolation and decimation factor
+SamplesPerCycle = str2double(get_param([bdroot '/RF Data Converter'], ...
+    'dacSamplesPerCycle')); % samples per FPGA cycle

utilities/soc_rfsoc_preload.m

@@ -0,0 +1,10 @@
+%% DMA and SW parameters
+FrameSize = 512;
+NumBuffers = 16;
+
+%% Rate setup (use txspectrum and rxspectrum tools)
+
+% local
+fs_RF = 4096e6; % RF data converter sampling rate
+fs_RF_MSPS = fs_RF/1e6; % Parameter on block is in Mega samples/s
+RFDC_NCOFreq_GHz = 0.768; % RFDC's NCO frequency in Giga Hertz

utilities/soc_rfsoc_prj_startup.m

@@ -3,4 +3,6 @@
 % Configure HDL Coder to use Xilinx Vivado for HDL workflows.
 %
 hdlsetuptoolpath('ToolName','Xilinx Vivado', ...
-                 'ToolPath','/tools/Xilinx/Vivado/2024.1/bin/vivado');
+                 'ToolPath','/tools/Xilinx/Vivado/2024.1/bin/vivado');
+
+%%