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base: canisio:feature/capture-redesign
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canisio:main canisio:feature/ps-frft canisio:feature/capture-redesign
canisio:v2.1 canisio:v2.0 canisio:v1.1 canisio:v1.0
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compare: canisio:1622f922f9c3e4e3b526f8a39387aca666dd1444
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canisio:feature/ps-frft canisio:main canisio:feature/capture-redesign
canisio:v2.1 canisio:v2.0 canisio:v1.1 canisio:v1.0

8 Commits
feature/ca ... 1622f922f9

Author SHA1 Message Date
canisio
1622f922f9 MeanPowSpec validated on board 2026-04-29 17:07:10 -03:00
canisio
041218aa7f test MeanPowSpec on ZCU111 2026-04-29 16:35:55 -03:00
canisio
d9f7798814 Added Mean Power Spectrum calculation on PS 2026-04-29 16:10:21 -03:00
canisio
1ab873419e clean version after tagging 2026-04-29 14:11:51 -03:00
canisio
65cef793ac Removed RMS and Fmax outputs 
Formatted top diagrams
 2026-04-29 11:30:02 -03:00
canisio
99c6b62fc6 Added CwMode as toggle switch 2026-04-29 10:44:14 -03:00
canisio
dc76c69731 added folder "codegen_frft" to the project (it was renamed) 2026-04-29 10:21:17 -03:00
canisio
1d0309f060 Merge branch 'feature/capture-redesign': Integrate capture redesign (multi-frame DMA + validation) 
- Redesigned capture pipeline for multi-frame acquisition
- Added 128-bit packing and correct endianness handling
- Implemented and validated counter-based integrity checks
- Verified bypass, channelizer, and pulsed signal modes
- Validated scaling up to nFrames=1024 on ZCU111
- Added checkCounterSamples.m for end-to-end validation

This establishes a stable and validated acquisition baseline for
future work (timestamping, UDP streaming, FrFT processing).
 2026-04-29 10:15:07 -03:00
17 changed files with 48 additions and 24 deletions
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gm_soc_rfsoc_top_sw.slx
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<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft/codegen/mex/fracF_cg/interface" Type="Relative"/>

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<Info Ref="codegen_frft/codegen" Type="Relative"/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft/codegen/mex" Type="Relative"/>

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utilities/soc_rfsoc_init.m
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@@ -24,8 +24,8 @@ NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);
%% Test signal parameters
% Pulse start/end frequencies
pulseCentFreq = 0e6;
pulseBw = 50e6; % Pulse bandwidth
%pulseCentFreq = 0e6;
pulseBw = 40e6; % Pulse bandwidth
% Number of pulses
numPulses = 10;
@@ -36,26 +36,30 @@ PRI = 1/PRF;
% Pulse time duration
%pulseT = 10; % use very long pulse help emulate CW
pulseT = 10e-6;
pulseT = 20e-6;
% CW mode (bypass pulse generation)
CwMode = false;
%CwMode = false;
% Counter mode (bypass pulse and CW generation)
CounterMode = true;
%CounterMode = true;
% Output gain
pulseGenGain = 1;
%% Software parameters
%% Simulation/External Mode parameters (conditional)
bd = bdroot; % Retrive which model is calling this function
% Signal generator update rate
switch bd
case 'soc_rfsoc_top'
TsSW = 0.0005; % Signal generator and capture update rate
StopTime = 0.025; % Simulation total time
case 'gm_soc_rfsoc_top_sw'
TsSW = 0.5;
%% Simulation parameters
% Sim run time
%stoptime = TsFPGA*(9 + 1*348 + 1 + 2*128 + 1); %10*TsSW; %TsFPGA*(1*128+348)
StopTime = 60;
otherwise
error('rfsoc_init: InvalidModel (%s not supported).', bd);
end
%% Channelizer parameters