20 Commits

Author SHA1 Message Date
canisio
2428f5a861 FrFT DPW processing validade in terms of dimensions and code generation 2026-06-09 16:18:00 -03:00
canisio
f64f4fde31 Added codegen folder and scripts for fracF operating in DPW (matrix) 2026-06-09 16:15:39 -03:00
canisio
22c51e1597 FrFT not working (for each error) 2026-06-09 14:54:59 -03:00
canisio
23a3503cb1 initialization of pulse center freq. 2026-06-09 10:51:09 -03:00
canisio
21c46dc45e removed subfolders codegen_frft 2026-05-22 15:58:53 -03:00
canisio
99ffaa1bfc startup funcion adapted to non-vivado machines 2026-05-22 15:42:32 -03:00
canisio
48bbb7102a first tests on FrFT 2026-05-22 12:57:30 -03:00
canisio
b57260583a fft of FrFT block changed from FFTW to auto 2026-05-21 17:30:38 -03:00
canisio
8839674480 renamed the scopes to differentiate sim to hw 2026-05-21 17:22:52 -03:00
canisio
005d488d79 Added variant subsystem and placeholder for FrFT. Simulation OK. External gives error 2026-05-19 17:19:30 -03:00
canisio
baedad87fa NEON optimization enabled for C code generation on both proc and interface models 2026-04-30 17:39:17 -03:00
canisio
19fd4dfb2d second validation of MeanPowSpec before branch to FrFT. Created slides on interface and tested several combinations of paramters. Resulds within expected. 2026-04-30 12:24:24 -03:00
canisio
1622f922f9 MeanPowSpec validated on board 2026-04-29 17:07:10 -03:00
canisio
041218aa7f test MeanPowSpec on ZCU111 2026-04-29 16:35:55 -03:00
canisio
d9f7798814 Added Mean Power Spectrum calculation on PS 2026-04-29 16:10:21 -03:00
canisio
1ab873419e clean version after tagging 2026-04-29 14:11:51 -03:00
canisio
65cef793ac Removed RMS and Fmax outputs
Formatted top diagrams
2026-04-29 11:30:02 -03:00
canisio
99c6b62fc6 Added CwMode as toggle switch 2026-04-29 10:44:14 -03:00
canisio
dc76c69731 added folder "codegen_frft" to the project (it was renamed) 2026-04-29 10:21:17 -03:00
canisio
1d0309f060 Merge branch 'feature/capture-redesign': Integrate capture redesign (multi-frame DMA + validation)
- Redesigned capture pipeline for multi-frame acquisition
- Added 128-bit packing and correct endianness handling
- Implemented and validated counter-based integrity checks
- Verified bypass, channelizer, and pulsed signal modes
- Validated scaling up to nFrames=1024 on ZCU111
- Added checkCounterSamples.m for end-to-end validation

This establishes a stable and validated acquisition baseline for
future work (timestamping, UDP streaming, FrFT processing).
2026-04-29 10:15:07 -03:00
32 changed files with 252 additions and 33 deletions

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@@ -0,0 +1,20 @@
a = single(1);
[Achirp,AchirpOut,H,scale] = fracF_init(a);
X = complex(randn(1024,1024,'single'), ...
randn(1024,1024,'single'));
Fdpw = fracF_dpw(X,...
Achirp,...
AchirpOut,...
H,...
scale);
Fref = complex(zeros(512,64,'single'));
for k = 1:1024
Fref(:,k) = fracF_cg(X(:,k),a);
end
maxErr = max(abs(Fdpw(:)-Fref(:)))

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@@ -0,0 +1,51 @@
function F = fracF_dpw(f,...
Achirp,...
AchirpOut,...
H,...
scale)
%#codegen
%
% fracF_dpw
%
% Matrix FrFT processing for an entire DPW.
%
% INPUT:
% f [1024 x Nframes] complex(single)
% Achirp [1024 x 1]
% AchirpOut [512 x 1]
% H [2048 x 1]
% scale scalar
%
% OUTPUT:
% F [512 x Nframes]
N = 1024;
Nfft = 2048;
Nframes = size(f,2);
%% First chirp multiplication
g = f .* Achirp;
%% Zero-padding
g_pad = complex(zeros(Nfft,Nframes,'single'));
g_pad(1:N,:) = g;
%% FFT convolution
Gfft = fft(g_pad);
G = ifft(Gfft .* H);
%% Extract valid region and decimate
G_valid = G(N+1:2:end,:);
%% Final chirp multiplication
F = scale .* G_valid .* AchirpOut;
end

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@@ -0,0 +1,70 @@
function [Achirp,AchirpOut,H,scale] = fracF_init(a)
%#codegen
%
% fracF_init
%
% Precompute FrFT coefficients for DPW processing.
%
% INPUT:
% a - FrFT order (single)
%
% OUTPUTS:
% Achirp [1024 x 1]
% AchirpOut [512 x 1]
% H [2048 x 1]
% scale scalar
N = 1024;
pi_s = single(pi);
phi = a * (pi_s/2);
tan_half_phi = tan(phi/2);
sin_phi = sin(phi);
cos_phi = cos(phi);
csc_phi = 1/sin_phi;
cot_phi = cos_phi/sin_phi;
twoDelta = 2*sqrt(single(N)/2);
%% Chirp A
n = single((-N/2:N/2-1).') / twoDelta;
Achirp = exp(-1j*pi_s*(n.^2)*tan_half_phi);
%% Chirp B
m = single((-N:N-1).') / twoDelta;
Bchirp = exp(1j*pi_s*csc_phi*(m.^2));
%% FFT of Chirp B
H = fft(Bchirp);
%% Output chirp
AchirpOut = Achirp(1:2:end);
%% Scale factor
scale = sqrt(1 - 1j*cot_phi) / twoDelta;
%% Force single precision complex
Achirp = complex(single(real(Achirp)), ...
single(imag(Achirp)));
AchirpOut = complex(single(real(AchirpOut)), ...
single(imag(AchirpOut)));
H = complex(single(real(H)), ...
single(imag(H)));
scale = complex(single(real(scale)), ...
single(imag(scale)));
end

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@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_fracFdpw" Type="Relative"/>

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@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="1617913e-1a81-4c05-b67f-42a35e5cd27b" type="Reference"/>

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@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft" Type="Relative"/>

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@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="e5067e19-daed-4732-909a-6dc210e105d6" type="Reference"/>

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@@ -1,2 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="a92ac691-f104-48a3-8517-c0b00eec410f" type="Reference"/>

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@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="c2875307-deb1-4e40-b64d-d77c1eb908cb" type="Reference"/>

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@@ -0,0 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info>
<Category UUID="FileClassCategory">
<Label UUID="design"/>
</Category>
</Info>

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@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="fracF_dpw.m" type="File"/>

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@@ -0,0 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info>
<Category UUID="FileClassCategory">
<Label UUID="design"/>
</Category>
</Info>

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@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="TBm_fracFdpw.slx" type="File"/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info/>

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@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="1" type="DIR_SIGNIFIER"/>

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@@ -0,0 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info>
<Category UUID="FileClassCategory">
<Label UUID="design"/>
</Category>
</Info>

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@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="fracF_init.m" type="File"/>

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@@ -0,0 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info>
<Category UUID="FileClassCategory">
<Label UUID="design"/>
</Category>
</Info>

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@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="TBc_fracFdpw.m" type="File"/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info/>

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@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="codegen_fracFdpw" type="File"/>

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@@ -25,7 +25,7 @@ NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);
% Pulse start/end frequencies % Pulse start/end frequencies
pulseCentFreq = 0e6; pulseCentFreq = 0e6;
pulseBw = 50e6; % Pulse bandwidth pulseBw = 32e6; % Pulse bandwidth
% Number of pulses % Number of pulses
numPulses = 10; numPulses = 10;
@@ -34,28 +34,33 @@ numPulses = 10;
PRF = 7.5e3; PRF = 7.5e3;
PRI = 1/PRF; PRI = 1/PRF;
% Pulse time duration % Pulse time duration
%pulseT = 10; % use very long pulse help emulate CW %pulseT = 10; % use very long pulse help emulate CW
pulseT = 10e-6; pulseT = 32e-6;
% CW mode (bypass pulse generation) % CW mode (bypass pulse generation)
CwMode = false; %CwMode = false;
% Counter mode (bypass pulse and CW generation) % Counter mode (bypass pulse and CW generation)
CounterMode = true; %CounterMode = true;
% Output gain % Output gain
pulseGenGain = 1; pulseGenGain = 1;
%% Software parameters %% Simulation/External Mode parameters (conditional)
bd = bdroot; % Retrive which model is calling this function
% Signal generator update rate switch bd
TsSW = 0.5; case 'soc_rfsoc_top'
TsSW = 0.0005; % Signal generator and capture update rate
%% Simulation parameters StopTime = 0.025; % Simulation total time
case 'gm_soc_rfsoc_top_sw'
% Sim run time TsSW = 0.25;
%stoptime = TsFPGA*(9 + 1*348 + 1 + 2*128 + 1); %10*TsSW; %TsFPGA*(1*128+348) StopTime = 250;
otherwise
error('rfsoc_init: InvalidModel (%s not supported).', bd);
end
%% Channelizer parameters %% Channelizer parameters
@@ -78,8 +83,17 @@ channelizerCoeffs = channelizer.coeffs.Numerator;
%Starting frequency for each channel %Starting frequency for each channel
%chanFStart = chanBW/2:chanBW:(fs/2-chanBW/2); %chanFStart = chanBW/2:chanBW:(fs/2-chanBW/2);
%Number of frames in the DPW %% Frame and DPW capture parameters
nFrames = 1024;%nChan/SamplesPerCycle; samplesFrame = 512; % number of samples in one frame
TFrame = samplesFrame*Ts_eff; % time duration of a frame
%Number of frames in the DPW
nFrames = 1024;
%% FrFT tests
pulseBeta = pulseBw/pulseT; % chirp-rate in Hz/s
aMatch = -(2/pi)*(atan(fs_eff/(pulseBeta*TFrame)));
%aMatch = -(2/pi)*(atan(fs_eff/(pulseBw*pulseT)));
% Frame size after serializing x2
%frameSize = SamplesPerCycle/2;

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@@ -1,8 +1,24 @@
%% Startup Tasks %% Startup Tasks
% %
% Configure HDL Coder to use Xilinx Vivado for HDL workflows. % Configure HDL Coder to use Xilinx Vivado for HDL workflows
% only when Vivado is installed on this machine.
% %
hdlsetuptoolpath('ToolName','Xilinx Vivado', ...
'ToolPath','/tools/Xilinx/Vivado/2024.1/bin/vivado');
%% vivadoPath = '/tools/Xilinx/Vivado/2024.1/bin/vivado';
if exist(vivadoPath, 'file') == 2
hdlsetuptoolpath( ...
'ToolName', 'Xilinx Vivado', ...
'ToolPath', vivadoPath);
fprintf('[FrFT Project] Vivado detected. HDL workflow enabled.\n');
else
warning([ ...
'[FrFT Project] Vivado not found.\n' ...
'HDL synthesis / bitstream generation disabled.\n' ...
'Project running in MATLAB/Simulink modeling-only mode.']);
end