FrFT DPW processing validade in terms of dimensions and code generation

Formatted top diagrams

codegen_fracFdpw/TBc_fracFdpw.m

@@ -0,0 +1,20 @@
+a = single(1);
+
+[Achirp,AchirpOut,H,scale] = fracF_init(a);
+
+X = complex(randn(1024,1024,'single'), ...
+            randn(1024,1024,'single'));
+
+Fdpw = fracF_dpw(X,...
+                 Achirp,...
+                 AchirpOut,...
+                 H,...
+                 scale);
+
+Fref = complex(zeros(512,64,'single'));
+
+for k = 1:1024
+    Fref(:,k) = fracF_cg(X(:,k),a);
+end
+
+maxErr = max(abs(Fdpw(:)-Fref(:)))

codegen_fracFdpw/fracF_dpw.m

@@ -0,0 +1,51 @@
+function F = fracF_dpw(f,...
+                       Achirp,...
+                       AchirpOut,...
+                       H,...
+                       scale)
+%#codegen
+%
+% fracF_dpw
+%
+% Matrix FrFT processing for an entire DPW.
+%
+% INPUT:
+%   f          [1024 x Nframes] complex(single)
+%   Achirp     [1024 x 1]
+%   AchirpOut  [512  x 1]
+%   H          [2048 x 1]
+%   scale      scalar
+%
+% OUTPUT:
+%   F          [512 x Nframes]
+
+N    = 1024;
+Nfft = 2048;
+
+Nframes = size(f,2);
+
+%% First chirp multiplication
+
+g = f .* Achirp;
+
+%% Zero-padding
+
+g_pad = complex(zeros(Nfft,Nframes,'single'));
+
+g_pad(1:N,:) = g;
+
+%% FFT convolution
+
+Gfft = fft(g_pad);
+
+G = ifft(Gfft .* H);
+
+%% Extract valid region and decimate
+
+G_valid = G(N+1:2:end,:);
+
+%% Final chirp multiplication
+
+F = scale .* G_valid .* AchirpOut;
+
+end

codegen_fracFdpw/fracF_init.m

@@ -0,0 +1,70 @@
+function [Achirp,AchirpOut,H,scale] = fracF_init(a)
+%#codegen
+%
+% fracF_init
+%
+% Precompute FrFT coefficients for DPW processing.
+%
+% INPUT:
+%   a  - FrFT order (single)
+%
+% OUTPUTS:
+%   Achirp     [1024 x 1]
+%   AchirpOut  [512  x 1]
+%   H          [2048 x 1]
+%   scale      scalar
+
+N    = 1024;
+
+pi_s = single(pi);
+
+phi = a * (pi_s/2);
+
+tan_half_phi = tan(phi/2);
+sin_phi      = sin(phi);
+cos_phi      = cos(phi);
+
+csc_phi = 1/sin_phi;
+cot_phi = cos_phi/sin_phi;
+
+twoDelta = 2*sqrt(single(N)/2);
+
+%% Chirp A
+
+n = single((-N/2:N/2-1).') / twoDelta;
+
+Achirp = exp(-1j*pi_s*(n.^2)*tan_half_phi);
+
+%% Chirp B
+
+m = single((-N:N-1).') / twoDelta;
+
+Bchirp = exp(1j*pi_s*csc_phi*(m.^2));
+
+%% FFT of Chirp B
+
+H = fft(Bchirp);
+
+%% Output chirp
+
+AchirpOut = Achirp(1:2:end);
+
+%% Scale factor
+
+scale = sqrt(1 - 1j*cot_phi) / twoDelta;
+
+%% Force single precision complex
+
+Achirp    = complex(single(real(Achirp)), ...
+                    single(imag(Achirp)));
+
+AchirpOut = complex(single(real(AchirpOut)), ...
+                    single(imag(AchirpOut)));
+
+H         = complex(single(real(H)), ...
+                    single(imag(H)));
+
+scale     = complex(single(real(scale)), ...
+                    single(imag(scale)));
+
+end

codegen_frft/TBc_lfm_fracF.m

@@ -1,4 +1,4 @@
-%% FrFT Validation Script (Reference vs Original)
+  %% FrFT Validation Script (Reference vs Original)
 % Author: Canisio Barth
 
 clear; clc; close all;

docs/pl_tx_subsystem.md

@@ -18,16 +18,16 @@ and operates deterministically in the PL after a trigger from the PS.
 
 ## Architecture
 
-TxPulseStart (PS)
+TxPulseStart (PS)  
-        ↓
+        ↓  
-pulse_gen_ctrl (FSM)
+pulse_gen_ctrl (FSM)  
-        ↓
+        ↓  
-   tx_active
+   tx_active  
-        ↓
+        ↓  
-Phase Increment Logic
+Phase Increment Logic  
-        ↓
+        ↓  
-      NCO (DDS)
+      NCO (DDS)  
-        ↓
+        ↓  
    Complex Output (I/Q)
 
 ---

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/0W-QdLjPl5JXWY5WJJ8XuZdPRxsd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info Ref="codegen_fracFdpw" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/0W-QdLjPl5JXWY5WJJ8XuZdPRxsp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="1617913e-1a81-4c05-b67f-42a35e5cd27b" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/JbwyBYXD6u7N2R9cFCqk-kUly6Ed.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info Ref="codegen_frft" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/JbwyBYXD6u7N2R9cFCqk-kUly6Ep.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="e5067e19-daed-4732-909a-6dc210e105d6" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/XNALo81LXKoPpl_sWox0XlMZwrgp.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="a92ac691-f104-48a3-8517-c0b00eec410f" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/yHR9AGbyWFGhYHIDxoJYqebuMa8p.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="c2875307-deb1-4e40-b64d-d77c1eb908cb" type="Reference"/>

resources/project/SDMLmaWG7GHkKoV_kJ80kV-luys/1X5PSVWg8jp3h1SyNiJtJmD4jnQd.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info>
+    <Category UUID="FileClassCategory">
+        <Label UUID="design"/>
+    </Category>
+</Info>

resources/project/SDMLmaWG7GHkKoV_kJ80kV-luys/1X5PSVWg8jp3h1SyNiJtJmD4jnQp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="fracF_dpw.m" type="File"/>

resources/project/SDMLmaWG7GHkKoV_kJ80kV-luys/GIFBHwpY7Mj_mw96S-Wz-4P1djYd.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info>
+    <Category UUID="FileClassCategory">
+        <Label UUID="design"/>
+    </Category>
+</Info>

resources/project/SDMLmaWG7GHkKoV_kJ80kV-luys/GIFBHwpY7Mj_mw96S-Wz-4P1djYp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="TBm_fracFdpw.slx" type="File"/>

resources/project/SDMLmaWG7GHkKoV_kJ80kV-luys/VdNularF-Bizb3hmjaa7F00asGMd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/SDMLmaWG7GHkKoV_kJ80kV-luys/VdNularF-Bizb3hmjaa7F00asGMp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="1" type="DIR_SIGNIFIER"/>

resources/project/SDMLmaWG7GHkKoV_kJ80kV-luys/_GBXjYOPGNzpaGXZHNU9eBKs2y4d.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info>
+    <Category UUID="FileClassCategory">
+        <Label UUID="design"/>
+    </Category>
+</Info>

resources/project/SDMLmaWG7GHkKoV_kJ80kV-luys/_GBXjYOPGNzpaGXZHNU9eBKs2y4p.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="fracF_init.m" type="File"/>

resources/project/SDMLmaWG7GHkKoV_kJ80kV-luys/rFgbE7J0q1IfyjFFVSXP14Sbh30d.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info>
+    <Category UUID="FileClassCategory">
+        <Label UUID="design"/>
+    </Category>
+</Info>

resources/project/SDMLmaWG7GHkKoV_kJ80kV-luys/rFgbE7J0q1IfyjFFVSXP14Sbh30p.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="TBc_fracFdpw.m" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/SDMLmaWG7GHkKoV_kJ80kV-luysd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/SDMLmaWG7GHkKoV_kJ80kV-luysp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="codegen_fracFdpw" type="File"/>

utilities/soc_rfsoc_init.m

@@ -25,7 +25,7 @@ NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);
 
 % Pulse start/end frequencies
 pulseCentFreq = 0e6;
-pulseBw = 50e6; % Pulse bandwidth
+pulseBw = 32e6; % Pulse bandwidth
 
 % Number of pulses
 numPulses = 10;
@@ -34,28 +34,33 @@ numPulses = 10;
 PRF = 7.5e3;
 PRI = 1/PRF;
 
+
 % Pulse time duration
 %pulseT = 10; % use very long pulse help emulate CW
-pulseT = 10e-6;
+pulseT = 32e-6;
 
 % CW mode (bypass pulse generation)
-CwMode = false;
+%CwMode = false;
 
 % Counter mode (bypass pulse and CW generation)
-CounterMode = true;
+%CounterMode = true;
 
 % Output gain
 pulseGenGain = 1;
 
-%% Software parameters
+%% Simulation/External Mode parameters (conditional)
+bd = bdroot; % Retrive which model is calling this function
 
-% Signal generator update rate
+switch bd
-TsSW = 0.5;
+    case 'soc_rfsoc_top'
-
+        TsSW = 0.0005; % Signal generator and capture update rate
-%% Simulation parameters
+        StopTime = 0.025; % Simulation total time
-
+    case 'gm_soc_rfsoc_top_sw'
-% Sim run time
+        TsSW = 0.25;
-%stoptime = TsFPGA*(9 + 1*348 + 1 + 2*128 + 1); %10*TsSW; %TsFPGA*(1*128+348)
+        StopTime = 250;
+    otherwise
+        error('rfsoc_init: InvalidModel (%s not supported).', bd);
+end
 
 %% Channelizer parameters
 
@@ -78,8 +83,17 @@ channelizerCoeffs = channelizer.coeffs.Numerator;
 %Starting frequency for each channel
 %chanFStart = chanBW/2:chanBW:(fs/2-chanBW/2);
 
-%Number of frames in the DPW
+%% Frame and DPW capture parameters 
-nFrames = 1024;%nChan/SamplesPerCycle;
+samplesFrame = 512; % number of samples in one frame
+
+TFrame = samplesFrame*Ts_eff; % time duration of a frame
+
+%Number of frames in the DPW
+nFrames = 1024;
+
+%% FrFT tests
+pulseBeta = pulseBw/pulseT; % chirp-rate in Hz/s
+
+aMatch = -(2/pi)*(atan(fs_eff/(pulseBeta*TFrame)));
+%aMatch = -(2/pi)*(atan(fs_eff/(pulseBw*pulseT)));
 
-% Frame size after serializing x2
-%frameSize = SamplesPerCycle/2;

utilities/soc_rfsoc_prj_startup.m

@@ -1,8 +1,24 @@
 %% Startup Tasks
 %
-% Configure HDL Coder to use Xilinx Vivado for HDL workflows.
+% Configure HDL Coder to use Xilinx Vivado for HDL workflows
+% only when Vivado is installed on this machine.
 %
-hdlsetuptoolpath('ToolName','Xilinx Vivado', ...
-                 'ToolPath','/tools/Xilinx/Vivado/2024.1/bin/vivado');
 
-%% 
+vivadoPath = '/tools/Xilinx/Vivado/2024.1/bin/vivado';
+
+if exist(vivadoPath, 'file') == 2
+
+    hdlsetuptoolpath( ...
+        'ToolName', 'Xilinx Vivado', ...
+        'ToolPath', vivadoPath);
+
+    fprintf('[FrFT Project] Vivado detected. HDL workflow enabled.\n');
+
+else
+
+    warning([ ...
+        '[FrFT Project] Vivado not found.\n' ...
+        'HDL synthesis / bitstream generation disabled.\n' ...
+        'Project running in MATLAB/Simulink modeling-only mode.']);
+
+end