6 Commits

Author SHA1 Message Date
canisio
d9f7798814 Added Mean Power Spectrum calculation on PS 2026-04-29 16:10:21 -03:00
canisio
1ab873419e clean version after tagging 2026-04-29 14:11:51 -03:00
canisio
65cef793ac Removed RMS and Fmax outputs
Formatted top diagrams
2026-04-29 11:30:02 -03:00
canisio
99c6b62fc6 Added CwMode as toggle switch 2026-04-29 10:44:14 -03:00
canisio
dc76c69731 added folder "codegen_frft" to the project (it was renamed) 2026-04-29 10:21:17 -03:00
canisio
1d0309f060 Merge branch 'feature/capture-redesign': Integrate capture redesign (multi-frame DMA + validation)
- Redesigned capture pipeline for multi-frame acquisition
- Added 128-bit packing and correct endianness handling
- Implemented and validated counter-based integrity checks
- Verified bypass, channelizer, and pulsed signal modes
- Validated scaling up to nFrames=1024 on ZCU111
- Added checkCounterSamples.m for end-to-end validation

This establishes a stable and validated acquisition baseline for
future work (timestamping, UDP streaming, FrFT processing).
2026-04-29 10:15:07 -03:00
17 changed files with 46 additions and 22 deletions

View File

@@ -1,4 +1,4 @@
%% FrFT Validation Script (Reference vs Original)
%% FrFT Validation Script (Reference vs Original)
% Author: Canisio Barth
clear; clc; close all;

Binary file not shown.

Binary file not shown.

Binary file not shown.

View File

@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft/codegen/mex/fracF_cg/interface" Type="Relative"/>

View File

@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="4a7e46c8-b608-4097-9e1f-6b08f40b724c" type="Reference"/>

View File

@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft" Type="Relative"/>

View File

@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="e5067e19-daed-4732-909a-6dc210e105d6" type="Reference"/>

View File

@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft/codegen" Type="Relative"/>

View File

@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="7593a6a4-6687-4364-8723-1bc8794d0177" type="Reference"/>

View File

@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft/codegen/mex" Type="Relative"/>

View File

@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="732585ee-100e-439f-988e-c97de5008a4c" type="Reference"/>

View File

@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft/codegen/mex/fracF_cg" Type="Relative"/>

View File

@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="81080468-b05c-494e-b13d-b9983b9ef350" type="Reference"/>

Binary file not shown.

View File

@@ -25,7 +25,7 @@ NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);
% Pulse start/end frequencies
pulseCentFreq = 0e6;
pulseBw = 50e6; % Pulse bandwidth
pulseBw = 0e6; % Pulse bandwidth
% Number of pulses
numPulses = 10;
@@ -39,23 +39,27 @@ PRI = 1/PRF;
pulseT = 10e-6;
% CW mode (bypass pulse generation)
CwMode = false;
%CwMode = false;
% Counter mode (bypass pulse and CW generation)
CounterMode = true;
%CounterMode = true;
% Output gain
pulseGenGain = 1;
%% Software parameters
%% Simulation/External Mode parameters (conditional)
bd = bdroot; % Retrive which model is calling this function
% Signal generator update rate
TsSW = 0.5;
%% Simulation parameters
% Sim run time
%stoptime = TsFPGA*(9 + 1*348 + 1 + 2*128 + 1); %10*TsSW; %TsFPGA*(1*128+348)
switch bd
case 'soc_rfsoc_top'
TsSW = 0.0005; % Signal generator and capture update rate
StopTime = 0.0025; % Simulation total time
case 'gm_soc_rfsoc_top_sw'
TsSW = 0.5;
StopTime = 10;
otherwise
error('rfsoc_init: InvalidModel (%s not supported).', bd);
end
%% Channelizer parameters