FrFT not working (for each error)

Formatted top diagrams

codegen_frft/TBc_lfm_fracF.m

@@ -1,4 +1,4 @@
-%% FrFT Validation Script (Reference vs Original)
+  %% FrFT Validation Script (Reference vs Original)
 % Author: Canisio Barth
 
 clear; clc; close all;

docs/pl_tx_subsystem.md

@@ -18,16 +18,16 @@ and operates deterministically in the PL after a trigger from the PS.
 
 ## Architecture
 
-TxPulseStart (PS)
-        ↓
-pulse_gen_ctrl (FSM)
-        ↓
-   tx_active
-        ↓
-Phase Increment Logic
-        ↓
-      NCO (DDS)
-        ↓
+TxPulseStart (PS)  
+        ↓  
+pulse_gen_ctrl (FSM)  
+        ↓  
+   tx_active  
+        ↓  
+Phase Increment Logic  
+        ↓  
+      NCO (DDS)  
+        ↓  
    Complex Output (I/Q)
 
 ---

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/JbwyBYXD6u7N2R9cFCqk-kUly6Ed.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info Ref="codegen_frft" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/JbwyBYXD6u7N2R9cFCqk-kUly6Ep.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="e5067e19-daed-4732-909a-6dc210e105d6" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/XNALo81LXKoPpl_sWox0XlMZwrgp.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="a92ac691-f104-48a3-8517-c0b00eec410f" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/yHR9AGbyWFGhYHIDxoJYqebuMa8p.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="c2875307-deb1-4e40-b64d-d77c1eb908cb" type="Reference"/>

utilities/soc_rfsoc_init.m

@@ -25,7 +25,7 @@ NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);
 
 % Pulse start/end frequencies
 pulseCentFreq = 0e6;
-pulseBw = 50e6; % Pulse bandwidth
+pulseBw = 32e6; % Pulse bandwidth
 
 % Number of pulses
 numPulses = 10;
@@ -34,28 +34,33 @@ numPulses = 10;
 PRF = 7.5e3;
 PRI = 1/PRF;
 
+
 % Pulse time duration
 %pulseT = 10; % use very long pulse help emulate CW
-pulseT = 10e-6;
+pulseT = 32e-6;
 
 % CW mode (bypass pulse generation)
-CwMode = false;
+%CwMode = false;
 
 % Counter mode (bypass pulse and CW generation)
-CounterMode = true;
+%CounterMode = true;
 
 % Output gain
 pulseGenGain = 1;
 
-%% Software parameters
+%% Simulation/External Mode parameters (conditional)
+bd = bdroot; % Retrive which model is calling this function
 
-% Signal generator update rate
-TsSW = 0.5;
-
-%% Simulation parameters
-
-% Sim run time
-%stoptime = TsFPGA*(9 + 1*348 + 1 + 2*128 + 1); %10*TsSW; %TsFPGA*(1*128+348)
+switch bd
+    case 'soc_rfsoc_top'
+        TsSW = 0.0005; % Signal generator and capture update rate
+        StopTime = 0.025; % Simulation total time
+    case 'gm_soc_rfsoc_top_sw'
+        TsSW = 0.25;
+        StopTime = 250;
+    otherwise
+        error('rfsoc_init: InvalidModel (%s not supported).', bd);
+end
 
 %% Channelizer parameters
 
@@ -78,8 +83,17 @@ channelizerCoeffs = channelizer.coeffs.Numerator;
 %Starting frequency for each channel
 %chanFStart = chanBW/2:chanBW:(fs/2-chanBW/2);
 
-%Number of frames in the DPW
-nFrames = 1024;%nChan/SamplesPerCycle;
+%% Frame and DPW capture parameters 
+samplesFrame = 512; % number of samples in one frame
+
+TFrame = samplesFrame*Ts_eff; % time duration of a frame
+
+%Number of frames in the DPW
+nFrames = 1024;
+
+%% FrFT tests
+pulseBeta = pulseBw/pulseT; % chirp-rate in Hz/s
+
+aMatch = -(2/pi)*(atan(fs_eff/(pulseBeta*TFrame)));
+%aMatch = -(2/pi)*(atan(fs_eff/(pulseBw*pulseT)));
 
-% Frame size after serializing x2
-%frameSize = SamplesPerCycle/2;

utilities/soc_rfsoc_prj_startup.m

@@ -1,8 +1,24 @@
 %% Startup Tasks
 %
-% Configure HDL Coder to use Xilinx Vivado for HDL workflows.
+% Configure HDL Coder to use Xilinx Vivado for HDL workflows
+% only when Vivado is installed on this machine.
 %
-hdlsetuptoolpath('ToolName','Xilinx Vivado', ...
-                 'ToolPath','/tools/Xilinx/Vivado/2024.1/bin/vivado');
 
-%% 
+vivadoPath = '/tools/Xilinx/Vivado/2024.1/bin/vivado';
+
+if exist(vivadoPath, 'file') == 2
+
+    hdlsetuptoolpath( ...
+        'ToolName', 'Xilinx Vivado', ...
+        'ToolPath', vivadoPath);
+
+    fprintf('[FrFT Project] Vivado detected. HDL workflow enabled.\n');
+
+else
+
+    warning([ ...
+        '[FrFT Project] Vivado not found.\n' ...
+        'HDL synthesis / bitstream generation disabled.\n' ...
+        'Project running in MATLAB/Simulink modeling-only mode.']);
+
+end