FPGA Packer: Changed to uint128, changed endianess order of packing (selectors 4,3,2,1)

Removed FIFO serializer and implemented 128-bit AXI packing (4 samples/beat)
Added initial MultiFrameCapture FSM
Validated with counter input
Sine/channelizer validation pending (frame interpretation update needed)

docs/pl_rx_subsystem.md

@@ -86,10 +86,12 @@ Implementation typically uses:
 
 ### ADC Input
 - Sampling rate: 4096 MSPS
+- Data type: **fixdt(1,16,15)** (Q1.15 format)
 
 ### PFB Channelizer
 - Decimation: 8
 - Effective bandwidth: 512 MHz
+- Input and internal scaling aligned to Q1.15 domain
 
 ### FFT
 - Size: 512
@@ -103,10 +105,48 @@ Implementation typically uses:
 
 ---
 
+## Numeric Format and Scaling
+
+### System Standardization
+
+The signal chain was standardized to a **Q1.15 fixed-point format (fixdt(1,16,15))**:
+
+- DAC output uses Q1.15
+- ADC input is reinterpreted as Q1.15 (Same Stored Integer)
+- Channelizer input operates in this normalized domain
+
+---
+
+### Channelizer Output Scaling
+
+- Native channelizer output: **sFix25_En23**
+- Rescaled and quantized to: **fixdt(1,16,15)**
+
+This conversion:
+
+- Preserves signal dynamic range
+- Maximizes fractional precision
+- Uses rounding and saturation
+- Aligns with system-wide numeric format
+
+---
+
+### Data Width Reduction
+
+- Previous format: **50 bits per complex sample** (25 bits real + 25 bits imag)
+- New format: **32 bits per complex sample** (16 bits real + 16 bits imag)
+
+Benefits:
+
+- Reduced AXI bandwidth
+- Reduced FIFO usage
+- More efficient DMA transfers
+
+---
+
 ## AXI4-Stream Output
 
-- Data type: uint64
+- Data type: uint32 (packed complex: 16-bit real + 16-bit imag)
-- Packed real/imag
 - TLAST = frame boundary
 
 ---
@@ -114,7 +154,7 @@ Implementation typically uses:
 ## Data Format
 
 - Frame size: 512 samples
-- Complex values packed into uint64
+- Complex samples packed into 32-bit words
 
 ---
 
@@ -123,6 +163,7 @@ Implementation typically uses:
 - Fully streaming pipeline
 - High throughput
 - Deterministic latency
+- Consistent fixed-point scaling (Q1.15 end-to-end)
 - Supports dual-mode operation (channelizer / bypass)
 
 ---

docs/pl_tx_subsystem.md

@@ -1,4 +1,4 @@
-# 📡 PL Tx Subsystem (Pulse Generator)
+# 📡 PL Tx Subsystem (Pulse & Continuous LFM Generator)
 
 [🏠 Project Home](../README.md)
 
@@ -6,7 +6,7 @@
 
 ## Overview
 
-The Tx subsystem implements a **pulse-based Linear Frequency Modulated (LFM) chirp generator** using a DDS/NCO architecture in the FPGA (PL).
+The Tx subsystem implements a **pulse-based and continuous Linear Frequency Modulated (LFM) chirp generator** using a DDS/NCO architecture in the FPGA (PL).
 
 The generator produces **complex baseband output**:
 
@@ -24,7 +24,7 @@ pulse_gen_ctrl (FSM)
         ↓
    tx_active
         ↓
-Phase Increment Counter
+Phase Increment Logic
         ↓
       NCO (DDS)
         ↓
@@ -32,6 +32,39 @@ Phase Increment Counter
 
 ---
 
+## Operating Modes
+
+The subsystem now supports multiple Tx modes:
+
+### 1. Pulsed LFM (default)
+
+- Chirp generated only during pulse window
+- Phase resets at each pulse start
+- Standard radar burst operation
+
+---
+
+### 2. CW Mode (Continuous Wave)
+
+- `tx_active = 1` continuously
+- Generates a single-tone output
+- Achieved by setting constant phase increment
+
+---
+
+### 3. Continuous LFM (Workaround Implementation)
+
+- `tx_active` forced HIGH continuously  
+- A **1-cycle LOW pulse** is inserted periodically  
+- This LOW→HIGH transition **resets the NCO**
+
+Result:
+- Continuous chirp
+- Bounded bandwidth
+- Periodic repetition of LFM
+
+---
+
 ## Chirp Generation Principle
 
 The chirp is generated using a second-order phase accumulator:
@@ -72,7 +105,7 @@ States:
 
 ## Timing Behavior
 
-Within each PRI:
+### Pulsed Mode
 
 |<------ PRI ------>|
 |<-- pulse -->| idle |
@@ -80,7 +113,31 @@ Within each PRI:
 - tx_active = 1 → chirp output  
 - tx_active = 0 → output zero  
 
-Chirp is reset at each pulse start.
+---
+
+### Continuous LFM Mode
+
+tx_active behavior:
+
+1 1 1 1 1 0 1 1 1 1 ...
+
+- 1-cycle LOW inserted at end of chirp period  
+- Rising edge resets NCO  
+- Defines chirp repetition interval  
+
+---
+
+## CW / Continuous LFM Implementation Details
+
+- CW mode bypasses FSM output
+- A dedicated counter generates periodic reset pulses
+- Reset timing is based on `pulse_width_cycles`
+
+Important:
+
+- Reset pulse is exactly **1 clock cycle**
+- Ensures deterministic NCO restart
+- Decoupled from PRI/FSM timing
 
 ---
 
@@ -97,7 +154,19 @@ Chirp is reset at each pulse start.
 - Deterministic timing (128 MHz)
 - Efficient DDS (adder-based)
 - Complex output (I/Q)
-- Supports burst-mode radar operation
+- Supports:
+  - Pulsed radar mode
+  - Continuous wave (CW)
+  - Continuous LFM (periodic chirp)
+
+---
+
+## Design Notes
+
+- FSM controls **timing (when to transmit)**
+- NCO controls **frequency evolution**
+- Continuous LFM implemented via **tx_active edge reuse**
+- Minimal hardware overhead (no additional NCO logic)
 
 ---
 

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/DeBrFbiozgTzo2gRi0Fzfz_WGlUd.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info Ref="bypass_block" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/DeBrFbiozgTzo2gRi0Fzfz_WGlUp.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="088fd74d-4620-4cf8-826f-495fb91d19ae" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/LVo7B_RSfnAS3NsdARLSe9kcOFcd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info Ref="block_pulsegen" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/LVo7B_RSfnAS3NsdARLSe9kcOFcp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="6a9c972f-52d5-42e0-8c82-940b26905df7" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/SwCK9Vqjv5J_5sSeux-jDiWs9yod.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info Ref="block_bypass" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/SwCK9Vqjv5J_5sSeux-jDiWs9yop.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="f7229047-4926-407b-902a-a25e790af1a9" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/cFPMi6Z544-rzRDst3iKr2HT8EUd.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info Ref="pulsegen_block" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/cFPMi6Z544-rzRDst3iKr2HT8EUp.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="e221a7ac-a0f0-4b2d-8909-e0ce275dca2e" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/jZgU_Ahn9qjarKQXLgCdj2YqbVAd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info Ref="block_capture" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/jZgU_Ahn9qjarKQXLgCdj2YqbVAp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="c26ab781-2c03-423c-8199-bc6903e4e4f7" type="Reference"/>

resources/project/KAXfQgCar2Yb8zOxgvf9hdmLP1E/56kb5FnOKTsZzWZfCNaKoOqXNgsd.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info File="gm_soc_rfsoc_top_sw.slx" GroupUUID="default" Icon="" Name="Open Interface model" Type="Basic" Visible="1"/>

resources/project/KAXfQgCar2Yb8zOxgvf9hdmLP1E/56kb5FnOKTsZzWZfCNaKoOqXNgsp.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="881a1955-5626-41b7-9355-a04f7db84232" type="EntryPoint"/>

resources/project/QuVfFK49N05REJIAYZLQasz_VuM/Xx0UDP9sUzEZe711HBEUtl4YraYp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="TBm_capture.slx" type="File"/>

resources/project/bMFzsIHr-EVKQIO2sqeU-274_I8/6ogmP0ZksmbyaUjs5D-G7nePRvop.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="1" type="DIR_SIGNIFIER"/>

resources/project/bMFzsIHr-EVKQIO2sqeU-274_I8/aye6s7-kaYjVsTGx2onCoqYnyTUd.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info>
+    <Category UUID="FileClassCategory">
+        <Label UUID="design"/>
+    </Category>
+</Info>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/F2x-oreEzd1RuWtdF_H3bxSqbsMp.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="bypass_block" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/LpvpJ1uloVvE37aexyCWfqNpR8Ep.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="block_pulsegen" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/MEnu9bsvaE1ht88eLRvHOJK-Wu0p.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="pulsegen_block" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/QuVfFK49N05REJIAYZLQasz_VuMd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/QuVfFK49N05REJIAYZLQasz_VuMp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="block_capture" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/bMFzsIHr-EVKQIO2sqeU-274_I8d.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/bMFzsIHr-EVKQIO2sqeU-274_I8p.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="block_bypass" type="File"/>

utilities/soc_rfsoc_init.m

@@ -24,31 +24,37 @@ NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);
 %% Test signal parameters
 
 % Pulse width
-pulseWidth = 8.5e-6;
+pulseWidth = 0.001;%4e-6;
 
 % Pulse start/end frequencies
-pulseCentFreq = 125e6;
+pulseCentFreq = 0e6;
-pulseBw = 50e6; % Pulse bandwidth
+pulseBw = 0e6; % Pulse bandwidth
 
 % Number of pulses
-numPulses = 4;
+numPulses = 10;
 
 % Pulse repetition interval
 PRF = 20e3;
 PRI = 1/PRF;
 
+% CW mode (bypass pulse generation)
+CwMode = true;
+
+% Counter mode (bypass pulse and CW generation)
+CounterMode = true;
+
 % Output gain
 pulseGenGain = 1;
 
 %% Software parameters
 
 % Signal generator update rate
-TsSW = 0.0025;
+TsSW = 0.001;
 
 %% Simulation parameters
 
 % Sim run time
-stoptime = 10*TsSW;
+%stoptime = TsFPGA*(9 + 1*348 + 1 + 2*128 + 1); %10*TsSW; %TsFPGA*(1*128+348)
 
 %% Channelizer parameters
 
@@ -71,37 +77,8 @@ channelizerCoeffs = channelizer.coeffs.Numerator;
 %Starting frequency for each channel
 %chanFStart = chanBW/2:chanBW:(fs/2-chanBW/2);
 
-%Number of frames out of channelzier
+%Number of frames in the DPW
-nFrames = nChan/SamplesPerCycle;
+nFrames = 4;%nChan/SamplesPerCycle;
 
 % Frame size after serializing x2
 %frameSize = SamplesPerCycle/2;
-
-
-
-
-
-% function soc_rfsoc_init(mdlPath)
-% % Initialization fcn for the model. It sets the model-wide params
-% % which are derived based on sample rate.
-% 
-% % 'FrameSize and 'NumBuffers' variables are set during model
-% % PreLoadFcn callback into base workspace. These two variables should be
-% % changed directly at the MATLAB command
-% 
-% % FrameSize = evalin('base','FrameSize');
-% 
-% dacSampleRate = get_param([mdlPath '/RF Data Converter'], 'dacSampleRate');
-% dacSampleRate = evalin('base', dacSampleRate)*1e6;
-% dacSamplesPerCycle = str2double(get_param([mdlPath '/RF Data Converter'], 'dacSamplesPerCycle'));
-% dacInterpolationMode = str2double(get_param([mdlPath '/RF Data Converter'], 'interpolationMode'));
-% streamClkFrequency = dacSampleRate/(dacSamplesPerCycle*dacInterpolationMode);
-% 
-% SampleTime = 1/streamClkFrequency;
-% 
-% % derived model-wide variables set into base workspace.
-% assignin('base','FPGAClkRate', streamClkFrequency);
-% assignin('base','TsFPGA', SampleTime);
-% assignin('base','SamplesPerCycle', dacSamplesPerCycle);
-% assignin('base','IntDecFactor', dacInterpolationMode);
-% end