Multi-frame capture (trigger-controlled DPW) validated in testbench; added 128-bit packer replacing serializer, correct unpacking (SI reinterpret) and frame reconstruction verified (counter + PFB); implemented VALID gating (zero when idle) and AXI-aligned pipelining; nFrames parameterized in TB

Removed FIFO serializer and implemented 128-bit AXI packing (4 samples/beat)
Added initial MultiFrameCapture FSM
Validated with counter input
Sine/channelizer validation pending (frame interpretation update needed)

docs/pl_rx_subsystem.md

@@ -86,10 +86,12 @@ Implementation typically uses:
 
 ### ADC Input
 - Sampling rate: 4096 MSPS
+- Data type: **fixdt(1,16,15)** (Q1.15 format)
 
 ### PFB Channelizer
 - Decimation: 8
 - Effective bandwidth: 512 MHz
+- Input and internal scaling aligned to Q1.15 domain
 
 ### FFT
 - Size: 512
@@ -103,10 +105,48 @@ Implementation typically uses:
 
 ---
 
+## Numeric Format and Scaling
+
+### System Standardization
+
+The signal chain was standardized to a **Q1.15 fixed-point format (fixdt(1,16,15))**:
+
+- DAC output uses Q1.15
+- ADC input is reinterpreted as Q1.15 (Same Stored Integer)
+- Channelizer input operates in this normalized domain
+
+---
+
+### Channelizer Output Scaling
+
+- Native channelizer output: **sFix25_En23**
+- Rescaled and quantized to: **fixdt(1,16,15)**
+
+This conversion:
+
+- Preserves signal dynamic range
+- Maximizes fractional precision
+- Uses rounding and saturation
+- Aligns with system-wide numeric format
+
+---
+
+### Data Width Reduction
+
+- Previous format: **50 bits per complex sample** (25 bits real + 25 bits imag)
+- New format: **32 bits per complex sample** (16 bits real + 16 bits imag)
+
+Benefits:
+
+- Reduced AXI bandwidth
+- Reduced FIFO usage
+- More efficient DMA transfers
+
+---
+
 ## AXI4-Stream Output
 
-- Data type: uint64
+- Data type: uint32 (packed complex: 16-bit real + 16-bit imag)
-- Packed real/imag
 - TLAST = frame boundary
 
 ---
@@ -114,7 +154,7 @@ Implementation typically uses:
 ## Data Format
 
 - Frame size: 512 samples
-- Complex values packed into uint64
+- Complex samples packed into 32-bit words
 
 ---
 
@@ -123,6 +163,7 @@ Implementation typically uses:
 - Fully streaming pipeline
 - High throughput
 - Deterministic latency
+- Consistent fixed-point scaling (Q1.15 end-to-end)
 - Supports dual-mode operation (channelizer / bypass)
 
 ---

resources/project/KAXfQgCar2Yb8zOxgvf9hdmLP1E/56kb5FnOKTsZzWZfCNaKoOqXNgsd.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info File="gm_soc_rfsoc_top_sw.slx" GroupUUID="default" Icon="" Name="Open Interface model" Type="Basic" Visible="1"/>

resources/project/KAXfQgCar2Yb8zOxgvf9hdmLP1E/56kb5FnOKTsZzWZfCNaKoOqXNgsp.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="881a1955-5626-41b7-9355-a04f7db84232" type="EntryPoint"/>

utilities/soc_rfsoc_init.m

@@ -28,7 +28,7 @@ pulseWidth = 4e-6;
 
 % Pulse start/end frequencies
 pulseCentFreq = 100e6;
-pulseBw = 5e6; % Pulse bandwidth
+pulseBw = 10e6; % Pulse bandwidth
 
 % Number of pulses
 numPulses = 10;
@@ -46,12 +46,12 @@ pulseGenGain = 1;
 %% Software parameters
 
 % Signal generator update rate
-TsSW = 0.5e-3;
+TsSW = 0.00025;
 
 %% Simulation parameters
 
 % Sim run time
-stoptime = 10*TsSW;
+stoptime = TsFPGA*(9 + 1*348 + 1 + 2*128 + 1); %10*TsSW; %TsFPGA*(1*128+348)
 
 %% Channelizer parameters