14 Commits

19 changed files with 52 additions and 42 deletions

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@@ -1,4 +1,4 @@
%% FrFT Validation Script (Reference vs Original) %% FrFT Validation Script (Reference vs Original)
% Author: Canisio Barth % Author: Canisio Barth
clear; clc; close all; clear; clc; close all;

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@@ -18,16 +18,16 @@ and operates deterministically in the PL after a trigger from the PS.
## Architecture ## Architecture
TxPulseStart (PS) TxPulseStart (PS)
pulse_gen_ctrl (FSM) pulse_gen_ctrl (FSM)
tx_active tx_active
Phase Increment Logic Phase Increment Logic
NCO (DDS) NCO (DDS)
Complex Output (I/Q) Complex Output (I/Q)
--- ---

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@@ -1,2 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft/codegen/mex/fracF_cg/interface" Type="Relative"/>

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@@ -1,2 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="4a7e46c8-b608-4097-9e1f-6b08f40b724c" type="Reference"/>

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@@ -1,2 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft/codegen" Type="Relative"/>

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@@ -1,2 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="7593a6a4-6687-4364-8723-1bc8794d0177" type="Reference"/>

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@@ -1,2 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft/codegen/mex" Type="Relative"/>

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@@ -1,2 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="732585ee-100e-439f-988e-c97de5008a4c" type="Reference"/>

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@@ -1,2 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="a92ac691-f104-48a3-8517-c0b00eec410f" type="Reference"/>

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@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="c2875307-deb1-4e40-b64d-d77c1eb908cb" type="Reference"/>

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@@ -1,2 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="codegen_frft/codegen/mex/fracF_cg" Type="Relative"/>

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@@ -1,2 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<Info location="81080468-b05c-494e-b13d-b9983b9ef350" type="Reference"/>

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@@ -25,7 +25,7 @@ NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);
% Pulse start/end frequencies % Pulse start/end frequencies
pulseCentFreq = 0e6; pulseCentFreq = 0e6;
pulseBw = 50e6; % Pulse bandwidth pulseBw = 32e6; % Pulse bandwidth
% Number of pulses % Number of pulses
numPulses = 10; numPulses = 10;
@@ -34,9 +34,10 @@ numPulses = 10;
PRF = 7.5e3; PRF = 7.5e3;
PRI = 1/PRF; PRI = 1/PRF;
% Pulse time duration % Pulse time duration
%pulseT = 10; % use very long pulse help emulate CW %pulseT = 10; % use very long pulse help emulate CW
pulseT = 10e-6; pulseT = 32e-6;
% CW mode (bypass pulse generation) % CW mode (bypass pulse generation)
%CwMode = false; %CwMode = false;
@@ -53,10 +54,10 @@ bd = bdroot; % Retrive which model is calling this function
switch bd switch bd
case 'soc_rfsoc_top' case 'soc_rfsoc_top'
TsSW = 0.0005; % Signal generator and capture update rate TsSW = 0.0005; % Signal generator and capture update rate
StopTime = 0.0025; % Simulation total time StopTime = 0.025; % Simulation total time
case 'gm_soc_rfsoc_top_sw' case 'gm_soc_rfsoc_top_sw'
TsSW = 0.5; TsSW = 0.25;
StopTime = 10; StopTime = 250;
otherwise otherwise
error('rfsoc_init: InvalidModel (%s not supported).', bd); error('rfsoc_init: InvalidModel (%s not supported).', bd);
end end
@@ -82,8 +83,17 @@ channelizerCoeffs = channelizer.coeffs.Numerator;
%Starting frequency for each channel %Starting frequency for each channel
%chanFStart = chanBW/2:chanBW:(fs/2-chanBW/2); %chanFStart = chanBW/2:chanBW:(fs/2-chanBW/2);
%Number of frames in the DPW %% Frame and DPW capture parameters
nFrames = 1024;%nChan/SamplesPerCycle; samplesFrame = 512; % number of samples in one frame
TFrame = samplesFrame*Ts_eff; % time duration of a frame
%Number of frames in the DPW
nFrames = 1024;
%% FrFT tests
pulseBeta = pulseBw/pulseT; % chirp-rate in Hz/s
aMatch = -(2/pi)*(atan(fs_eff/(pulseBeta*TFrame)));
%aMatch = -(2/pi)*(atan(fs_eff/(pulseBw*pulseT)));
% Frame size after serializing x2
%frameSize = SamplesPerCycle/2;

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@@ -1,8 +1,24 @@
%% Startup Tasks %% Startup Tasks
% %
% Configure HDL Coder to use Xilinx Vivado for HDL workflows. % Configure HDL Coder to use Xilinx Vivado for HDL workflows
% only when Vivado is installed on this machine.
% %
hdlsetuptoolpath('ToolName','Xilinx Vivado', ...
'ToolPath','/tools/Xilinx/Vivado/2024.1/bin/vivado');
%% vivadoPath = '/tools/Xilinx/Vivado/2024.1/bin/vivado';
if exist(vivadoPath, 'file') == 2
hdlsetuptoolpath( ...
'ToolName', 'Xilinx Vivado', ...
'ToolPath', vivadoPath);
fprintf('[FrFT Project] Vivado detected. HDL workflow enabled.\n');
else
warning([ ...
'[FrFT Project] Vivado not found.\n' ...
'HDL synthesis / bitstream generation disabled.\n' ...
'Project running in MATLAB/Simulink modeling-only mode.']);
end