# 📡 RFSoC Channelizer + PS Processing (R-ESM Prototype)

## Overview

This project is based on the RFSoC SoC Blockset reference design, adapted as a prototype for a Radar Electronic Support Measures (R-ESM) receiver.

The system implements a high-throughput signal chain in the FPGA (PL) and performs frame-based processing in the processor (PS).

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## Current Status

- Tx subsystem: LFM pulse generator (DDS-based, complex output)
- Rx subsystem: fully functional channelizer pipeline (PFB-based)
- PL → PS interface: AXI4-Stream + DMA operational
- PS processing: frame-based algorithm (RMS + peak detection)

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## System Architecture

ADC → Channelizer (PFB, 512 bins)  
→ FFT_Capture (frame control)  
→ FIFO Serializer (4 FIFOs → 1 stream)  
→ AXI4-Stream (uint64)  
→ DMA (S2MM)  
→ PS Memory  
→ Processor Algorithm  

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## Key Parameters

- ADC Sampling Rate: 4096 MSPS  
- Decimation: 8  
- Effective BW: 512 MHz  
- Channels (FFT size): 512  
- Samples per clock: 4  
- FPGA clock: 128 MHz  
- Frame size (PS): 512 samples  

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## 📚 Documentation

### FPGA (PL)

- [Tx Subsystem (Pulse Generator)](docs/pl_tx_subsystem.md)
- [Rx Subsystem (Channelizer)](docs/pl_rx_subsystem.md)

### Processor (PS)

- [PS Subsystem](docs/ps_subsystem.md)

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## System Flow

Tx → Rx → PS

- Tx generates waveform  
- Rx captures and channelizes  
- PS processes frames  

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## Roadmap

1. Functional FrFT (PS)
2. Profiling
3. NEON optimization
4. Throughput tuning
5. PL acceleration

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## Key Takeaway

First make it work end-to-end, then make it fast.