# 📡 PL Rx Subsystem (Channelizer)

[🏠 Project Home](../README.md)

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## Overview

The Rx subsystem implements a **polyphase filter bank (PFB) channelizer** followed by FFT processing.

It converts wideband ADC input into frequency-domain channels and streams the result to the PS.

A **bypass path** is also available for raw data inspection and debugging.

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## Architecture

### Channelizer Path (default)

ADC
 ↓
PFB Channelizer (Decimation + Filtering)
 ↓
FFT (512 bins)
 ↓
FFT Capture
 ↓
FIFO Serializer (4 → 1)
 ↓
AXI4-Stream
 ↓
DMA

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### Bypass Path (Debug / Raw Data)

ADC
 ↓
Bypass Path
 ↓
FIFO / Serializer
 ↓
AXI4-Stream
 ↓
DMA

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## Bypass Functionality

The bypass allows direct observation of the input signal without channelization.

### Purpose

- Debugging and validation
- Access to raw ADC-domain data
- Comparison with channelized output
- Verification of downstream processing

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### Behavior

- Input data is routed directly to output
- No filtering or FFT applied
- Maintains same output interface (AXI4-Stream)

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### Selection Mechanism

A selector signal chooses between:

- Channelizer output (normal operation)
- Bypass output (raw data)

Implementation typically uses:
- Parallel paths
- Output switching logic

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## Processing Chain (Channelizer Mode)

### ADC Input
- Sampling rate: 4096 MSPS

### PFB Channelizer
- Decimation: 8
- Effective bandwidth: 512 MHz

### FFT
- Size: 512
- Produces frequency bins

### FFT Capture
- Controls frame boundaries

### FIFO Serializer
- Converts parallel streams into single stream

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## AXI4-Stream Output

- Data type: uint64
- Packed real/imag
- TLAST = frame boundary

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## Data Format

- Frame size: 512 samples
- Complex values packed into uint64

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## Key Characteristics

- Fully streaming pipeline
- High throughput
- Deterministic latency
- Supports dual-mode operation (channelizer / bypass)

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## 🔗 Related Components

- [🏠 Project Home](../README.md)
- [PL Tx Subsystem](pl_tx_subsystem.md)
- [PS Subsystem](ps_subsystem.md)