%%  Derived from preload
fs_eff = fs_RF/IntDecFactor; % Effective fs before interpolation / after decimation
Ts_eff = 1/fs_eff;

%% Host Sample Time in Simulation
%TsHost = 5e-5;

FPGAClkRate = fs_eff/SamplesPerCycle;
TsFPGA = 1/FPGAClkRate;
%% Tx signal generator parameters

% NCO accumulator word length
NCOAccumWL = 16;

% NCO phase increment scale factor
NCOIncScale = Ts_eff*2^NCOAccumWL;

% NCO phase increments datatype
NCOIncDT = numerictype(1,NCOAccumWL,0);

% NCO counter increment datatype
NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);

%% Test signal parameters

% Pulse width
pulseWidth = 8.5e-6;

% Pulse start/end frequencies
pulseCentFreq = 125e6;
pulseBw = 50e6; % Pulse bandwidth

% Number of pulses
numPulses = 4;

% Pulse repetition interval
PRF = 20e3;
PRI = 1/PRF;

% Output gain
pulseGenGain = 1;

%% Software parameters

% Signal generator update rate
TsSW = 1e-3;

%% Simulation parameters

% Sim run time
stoptime = 10*TsSW;

%% Channelizer parameters

%Number of channels, maximally decimated channelizer M/D=1
nChan = 512;

%Taps per band
nTapsPerBand = 16;

%Create channelizer object
channelizer = dsp.Channelizer('NumFrequencyBands',nChan,...
                             'DecimationFactor',nChan,...
                             'NumTapsPerBand',nTapsPerBand);
%Channelizer coefficients
channelizerCoeffs = channelizer.coeffs.Numerator;

%Channel bandwidth
%chanBW = fs/nChan;

%Starting frequency for each channel
%chanFStart = chanBW/2:chanBW:(fs/2-chanBW/2);

%Number of frames out of channelzier
nFrames = nChan/SamplesPerCycle;

% Frame size after serializing x2
%frameSize = SamplesPerCycle/2;





% function soc_rfsoc_init(mdlPath)
% % Initialization fcn for the model. It sets the model-wide params
% % which are derived based on sample rate.
% 
% % 'FrameSize and 'NumBuffers' variables are set during model
% % PreLoadFcn callback into base workspace. These two variables should be
% % changed directly at the MATLAB command
% 
% % FrameSize = evalin('base','FrameSize');
% 
% dacSampleRate = get_param([mdlPath '/RF Data Converter'], 'dacSampleRate');
% dacSampleRate = evalin('base', dacSampleRate)*1e6;
% dacSamplesPerCycle = str2double(get_param([mdlPath '/RF Data Converter'], 'dacSamplesPerCycle'));
% dacInterpolationMode = str2double(get_param([mdlPath '/RF Data Converter'], 'interpolationMode'));
% streamClkFrequency = dacSampleRate/(dacSamplesPerCycle*dacInterpolationMode);
% 
% SampleTime = 1/streamClkFrequency;
% 
% % derived model-wide variables set into base workspace.
% assignin('base','FPGAClkRate', streamClkFrequency);
% assignin('base','TsFPGA', SampleTime);
% assignin('base','SamplesPerCycle', dacSamplesPerCycle);
% assignin('base','IntDecFactor', dacInterpolationMode);
% end