canisio 4cbe3b5699 renamed array plots os gm model

2026-04-24 11:33:15 -03:00

..

soc_rfsoc_fpga.slx

changed to upper and lower halves after stream read. No difference (only first lane of 4x1 being read)

2026-04-23 15:26:22 -03:00

soc_rfsoc_proc.slx

renamed array plots os gm model

2026-04-24 11:33:15 -03:00