canisio b2ce956f41 Multi-frame capture integrated into full design with trigger-controlled DPW; AXI stream (uint32 [4x1]) and DMA framing aligned; fixed FSM termination condition (no overflow); validated end-to-end (PL→DMA→PS) using counter input for multiple nFrames

2026-04-17 17:03:34 -03:00

..

aux

Oganize preload and init functions and parameters (ongoing)

2026-04-04 15:16:58 -03:00

soc_rfsoc_init.m

Multi-frame capture integrated into full design with trigger-controlled DPW; AXI stream (uint32 [4x1]) and DMA framing aligned; fixed FSM termination condition (no overflow); validated end-to-end (PL→DMA→PS) using counter input for multiple nFrames

2026-04-17 17:03:34 -03:00

soc_rfsoc_postload.m

finished organization of init funcions and parameters

2026-04-04 16:05:17 -03:00

soc_rfsoc_preload.m

finished organization of init funcions and parameters

2026-04-04 16:05:17 -03:00

soc_rfsoc_prj_startup.m

Oganize preload and init functions and parameters (ongoing)

2026-04-04 15:16:58 -03:00

soc_rfsoc_shutdown.m

Initial

2026-03-24 12:44:45 -03:00