canisio ccc6b9cd73 Validate 16-bit Q1.15 Rx chain (baseline, partial validation) ...

Standardized ADC/DAC and channelizer input to fixdt(1,16,15)
Rescaled channelizer output from sFix25_En23 to 16-bit complex
Verified channelizer path and spectrum behavior in full simulation
Bypass path and datatype tuning (coefficients/output) pending validation

2026-04-13 17:47:08 -03:00

..

soc_rfsoc_fpga.slx

Validate 16-bit Q1.15 Rx chain (baseline, partial validation)

2026-04-13 17:47:08 -03:00

soc_rfsoc_proc.slx

Validate 16-bit Q1.15 Rx chain (baseline, partial validation)

2026-04-13 17:47:08 -03:00