canisio df335aac1e validation: verified capture pipeline in counter bypass, sine bypass, and sine channelizer modes (nFrames=8) ...

Validated end-to-end data integrity and visualization across all modes.

2026-04-25 12:58:22 -03:00

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soc_rfsoc_fpga.slx

Revert "Created valid_out for conter input test"

2026-04-24 17:25:45 -03:00

soc_rfsoc_proc.slx

validation: verified capture pipeline in counter bypass, sine bypass, and sine channelizer modes (nFrames=8)

2026-04-25 12:58:22 -03:00