canisio fc50e71ab5 AXI stream updated to uint32 [4x1] format; samples-per-frame aligned to nFrames×512; PS stream read configured accordingly; single-frame (nFrames=1) validated end-to-end (PL→DMA→PS) with correct unpacking and data integrity

2026-04-17 12:22:12 -03:00

..

soc_rfsoc_fpga.slx

AXI stream updated to uint32 [4x1] format; samples-per-frame aligned to nFrames×512; PS stream read configured accordingly; single-frame (nFrames=1) validated end-to-end (PL→DMA→PS) with correct unpacking and data integrity

2026-04-17 12:22:12 -03:00

soc_rfsoc_proc.slx

AXI stream updated to uint32 [4x1] format; samples-per-frame aligned to nFrames×512; PS stream read configured accordingly; single-frame (nFrames=1) validated end-to-end (PL→DMA→PS) with correct unpacking and data integrity

2026-04-17 12:22:12 -03:00