docs: update documentation for capture redesign and validation

docs/pl_rx_subsystem.md

@@ -6,11 +6,9 @@
 
 ## Overview
 
-The Rx subsystem implements a **polyphase filter bank (PFB) channelizer** followed by FFT processing.
+The Rx subsystem implements a **polyphase filter bank (PFB) channelizer** followed by FFT processing, a **bypass path**, and a **multi-frame capture pipeline**.
 
-It converts wideband ADC input into frequency-domain channels and streams the result to the PS.
-
-A **bypass path** is also available for raw data inspection and debugging.
+It converts wideband ADC input into frequency-domain channels (or raw samples via bypass) and streams the result to the PS.
 
 ---
 
@@ -18,67 +16,46 @@ A **bypass path** is also available for raw data inspection and debugging.
 
 ### Channelizer Path (default)
 
-ADC
- ↓
-PFB Channelizer (Decimation + Filtering)
- ↓
-FFT (512 bins)
- ↓
-FFT Capture
- ↓
-FIFO Serializer (4 → 1)
- ↓
-AXI4-Stream
- ↓
+ADC  
+ ↓  
+PFB Channelizer (Decimation + Filtering)  
+ ↓  
+FFT (512 bins)  
+ ↓  
+Capture (frame control)  
+ ↓  
+AXI4-Stream (128-bit, 4 samples/clock)  
+ ↓  
 DMA
 
 ---
 
 ### Bypass Path (Debug / Raw Data)
 
-ADC
- ↓
-Bypass Path
- ↓
-FIFO / Serializer
- ↓
-AXI4-Stream
- ↓
+ADC  
+ ↓  
+Bypass Path  
+ ↓  
+Capture (frame control)  
+ ↓  
+AXI4-Stream (128-bit, 4 samples/clock)  
+ ↓  
 DMA
 
 ---
 
-## Bypass Functionality
+## Capture Pipeline
 
-The bypass allows direct observation of the input signal without channelization.
-
-### Purpose
-
-- Debugging and validation
-- Access to raw ADC-domain data
-- Comparison with channelized output
-- Verification of downstream processing
-
----
+- Multi-frame acquisition (configurable nFrames)
+- Frame size: 512 samples
+- Supports asynchronous capture start (not frame-aligned)
+- TLAST asserted at frame boundaries
 
 ### Behavior
 
-- Input data is routed directly to output
-- No filtering or FFT applied
-- Maintains same output interface (AXI4-Stream)
-
----
-
-### Selection Mechanism
-
-A selector signal chooses between:
-
-- Channelizer output (normal operation)
-- Bypass output (raw data)
-
-Implementation typically uses:
-- Parallel paths
-- Output switching logic
+- First frame may be partial
+- Frames may contain ≤ 2 frame indices (expected)
+- DPW spans nFrames frames but covers nFrames + 1 frame regions
 
 ---
 
@@ -86,22 +63,19 @@ Implementation typically uses:
 
 ### ADC Input
 - Sampling rate: 4096 MSPS
-- Data type: **fixdt(1,16,15)** (Q1.15 format)
+- Data type: **fixdt(1,16,15)** (Q1.15)
 
 ### PFB Channelizer
 - Decimation: 8
 - Effective bandwidth: 512 MHz
-- Input and internal scaling aligned to Q1.15 domain
 
 ### FFT
 - Size: 512
 - Produces frequency bins
 
-### FFT Capture
-- Controls frame boundaries
-
-### FIFO Serializer
-- Converts parallel streams into single stream
+### Capture
+- Defines frame boundaries (512 samples)
+- Generates TLAST
 
 ---
 
@@ -109,62 +83,57 @@ Implementation typically uses:
 
 ### System Standardization
 
-The signal chain was standardized to a **Q1.15 fixed-point format (fixdt(1,16,15))**:
-
-- DAC output uses Q1.15
-- ADC input is reinterpreted as Q1.15 (Same Stored Integer)
-- Channelizer input operates in this normalized domain
-
----
+- End-to-end Q1.15 (**fixdt(1,16,15)**)
 
 ### Channelizer Output Scaling
 
-- Native channelizer output: **sFix25_En23**
-- Rescaled and quantized to: **fixdt(1,16,15)**
-
-This conversion:
-
-- Preserves signal dynamic range
-- Maximizes fractional precision
-- Uses rounding and saturation
-- Aligns with system-wide numeric format
+- Native: **sFix25_En23**
+- Quantized to: **fixdt(1,16,15)** (round + saturate)
 
 ---
 
-### Data Width Reduction
+## Data Packing (Updated)
 
-- Previous format: **50 bits per complex sample** (25 bits real + 25 bits imag)
-- New format: **32 bits per complex sample** (16 bits real + 16 bits imag)
+- 4 samples per clock
+- Each sample: complex (16-bit real + 16-bit imag)
+- Packed into **128-bit AXI4-Stream word**
 
 Benefits:
-
-- Reduced AXI bandwidth
-- Reduced FIFO usage
-- More efficient DMA transfers
+- Matches datapath parallelism
+- Efficient DMA transfers
+- Eliminates need for serializer stage
 
 ---
 
 ## AXI4-Stream Output
 
-- Data type: uint32 (packed complex: 16-bit real + 16-bit imag)
+- Width: 128 bits
+- Contains 4 complex samples per cycle
 - TLAST = frame boundary
 
 ---
 
-## Data Format
+## Debug / Validation Features
 
-- Frame size: 512 samples
-- Complex samples packed into 32-bit words
+A counter-based debug mode is implemented:
+
+- Real part → sample counter (0..511)
+- Imag part → frame index
+
+Used to validate:
+- Sample continuity
+- Frame boundaries
+- DMA ordering and integrity
 
 ---
 
 ## Key Characteristics
 
 - Fully streaming pipeline
-- High throughput
 - Deterministic latency
-- Consistent fixed-point scaling (Q1.15 end-to-end)
-- Supports dual-mode operation (channelizer / bypass)
+- High throughput (4 samples/clock)
+- Dual-mode operation (channelizer / bypass)
+- Validated up to nFrames = 1024
 
 ---