detailed subsystems
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canisio
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# 📡 PL Rx Subsystem (Channelizer)
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[🏠 Project Home](../README.md)
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---
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## Overview
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Implements PFB channelizer and FFT processing.
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The Rx subsystem implements a **polyphase filter bank (PFB) channelizer** followed by FFT processing.
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It converts wideband ADC input into frequency-domain channels.
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---
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## Architecture
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ADC → PFB → FFT → Capture → FIFO → AXI → DMA
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ADC
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↓
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PFB Channelizer (Decimation + Filtering)
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↓
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FFT (512 bins)
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↓
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FFT Capture
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↓
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FIFO Serializer (4 → 1)
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↓
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AXI4-Stream
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↓
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DMA
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---
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## Processing
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## Processing Chain
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- 4096 MSPS input
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- Decimation 8
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- FFT 512 bins
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### ADC Input
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- Sampling rate: 4096 MSPS
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### PFB Channelizer
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- Decimation: 8
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- Effective bandwidth: 512 MHz
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### FFT
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- Size: 512
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- Produces frequency bins
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### FFT Capture
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- Controls frame boundaries
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### FIFO Serializer
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- Converts parallel streams into single stream
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---
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## Output
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## AXI4-Stream Output
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- AXI4-Stream
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- uint64 format
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- TLAST per frame
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- Data type: uint64
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- Packed real/imag
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- TLAST = frame boundary
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---
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## Data Format
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- Frame size: 512 samples
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- Complex values packed into uint64
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---
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## Key Characteristics
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- Fully streaming pipeline
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- High throughput
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- Deterministic latency
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- DMA-ready output
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---
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## 🔗 Related Components
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- [Project Overview (README)](../README.md)
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- [🏠 Project Home](../README.md)
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- [PL Tx Subsystem](pl_tx_subsystem.md)
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- [PS Subsystem](ps_subsystem.md)
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# 📡 PL Tx Subsystem (Pulse Generator)
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[🏠 Project Home](../README.md)
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---
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## Overview
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The Tx subsystem implements a pulse-based LFM chirp generator using a DDS/NCO architecture.
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The Tx subsystem implements a **pulse-based Linear Frequency Modulated (LFM) chirp generator** using a DDS/NCO architecture in the FPGA (PL).
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The generator produces **complex baseband output**:
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x[n] = exp(j·φ[n])
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and operates deterministically in the PL after a trigger from the PS.
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---
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## Architecture
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TxPulseStart → pulse_gen_ctrl → tx_active → NCO → Output
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TxPulseStart (PS)
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↓
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pulse_gen_ctrl (FSM)
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↓
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tx_active
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↓
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Phase Increment Counter
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↓
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NCO (DDS)
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↓
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Complex Output (I/Q)
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---
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## Chirp Generation
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## Chirp Generation Principle
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The chirp is generated using a second-order phase accumulator:
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Δφ[n] = Δφ[n−1] + step
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φ[n] = φ[n−1] + Δφ[n]
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This results in a linear frequency sweep.
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---
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## Parameterization
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## Parameterization (PS → PL)
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- Fc (center frequency)
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- B (bandwidth)
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Inputs:
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- Center frequency: Fc
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- Bandwidth: B
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- Pulse width: N (samples)
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Derived internally:
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Derived:
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f_start = Fc − B/2
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step = B / (N − 1)
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These values are converted to DDS phase increments before being written to PL registers.
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---
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## Pulse Timing
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## Pulse Timing (FSM)
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States:
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- IDLE: waits for trigger and latches parameters
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- ACTIVE: generates pulses
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- DONE: waits for trigger reset
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---
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## Timing Behavior
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Within each PRI:
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|<------ PRI ------>|
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|<-- pulse -->| idle |
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- tx_active = 1 → chirp output
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- tx_active = 0 → output zero
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Chirp is reset at each pulse start.
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---
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## Trigger
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## Burst Trigger (PS Interaction)
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Controlled via TxPulseStart (from PS subsystem)
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- Controlled via TxPulseStart (memory-mapped register)
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- Rising edge triggers burst
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- PL runs autonomously afterward
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---
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## Key Characteristics
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- Deterministic timing (128 MHz)
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- Efficient DDS (adder-based)
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- Complex output (I/Q)
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- Supports burst-mode radar operation
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---
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## 🔗 Related Components
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- [Project Overview (README)](../README.md)
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- [PS Subsystem](ps_subsystem.md)
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- [🏠 Project Home](../README.md)
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- [PL Rx Subsystem](pl_rx_subsystem.md)
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- [PS Subsystem](ps_subsystem.md)
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@@ -1,33 +1,85 @@
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# 🧠 PS Subsystem
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# 🧠 PS Subsystem (Control + Processing)
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[🏠 Project Home](../README.md)
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---
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## Overview
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Handles control and processing.
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The PS subsystem is responsible for:
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- Configuring PL subsystems
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- Receiving data via DMA
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- Performing frame-based processing
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---
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## Control
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## Responsibilities
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- Writes parameters
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- Triggers Tx (TxPulseStart)
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### Control
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- Writes parameters to PL registers:
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- Tx generator configuration
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- Generates TxPulseStart trigger
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---
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## Processing
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### DMA Handling
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DMA → unpack → complex → RMS/peak
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- AXI4-Stream → DMA (S2MM)
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- Data stored in PS DDR
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Configuration:
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- Frame size: 512
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- Buffers: 16
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---
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## Execution
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### Processing Pipeline
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- Event-driven
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- Frame drops possible
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DMA → uint64[512]
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→ unpack real/imag
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→ convert to complex
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→ RMS + peak detection
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---
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## Execution Model
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- Event-driven (DMA trigger)
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- No buffering queue
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- Frames may be dropped
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---
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## Performance Notes
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- Bottleneck: unpacking + conversion
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- Cannot sustain full-rate input
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---
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## Interaction with PL
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### Tx Control
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- Low-rate trigger (~Hz)
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- Starts burst generation
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### Rx Data
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- Continuous high-rate stream
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---
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## Future Work
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- Replace processing with FrFT
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- NEON optimization
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- Throughput improvements
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---
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## 🔗 Related Components
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- [Project Overview (README)](../README.md)
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- [🏠 Project Home](../README.md)
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- [PL Tx Subsystem](pl_tx_subsystem.md)
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- [PL Rx Subsystem](pl_rx_subsystem.md)
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