diagram update (added PS)
This commit is contained in:
canisio
@@ -1,15 +1,15 @@
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@@ -17,14 +17,14 @@
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@@ -32,16 +32,19 @@
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<mxCell id="MkqXqfyG2YaBNjo1GXRg-10" parent="1" style="rounded=1;whiteSpace=wrap;html=1;" value="DAC<div>Data clock = 128MHz</div><div>4 Samples/clock</div><div>BW = 512MHz</div><div>Interpolation = 8X</div><div>Fs = 4096MHz</div>" vertex="1">
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<mxCell id="MkqXqfyG2YaBNjo1GXRg-12" parent="1" style="rounded=1;whiteSpace=wrap;html=1;" value="ADC<div>Fs = 4096MHz</div><div>Decimation = 8X</div><div>BW = 512MHz</div><div>4 Samples/clock</div><div>Data clock = 128MHz</div>" vertex="1">
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@@ -50,11 +53,11 @@
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@@ -62,6 +65,11 @@
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@@ -129,24 +137,24 @@
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@@ -154,6 +162,47 @@
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