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Added counter mode as input, real part = sample counter, imag part = frame counter. Reset on software trigger

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canisio
2026-04-21 12:25:21 -03:00
parent 78a7d1ae68
commit 4b1b94c424
4 changed files with 4 additions and 1 deletions
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referencedmodels/soc_rfsoc_fpga.slx
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referencedmodels/soc_rfsoc_proc.slx
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soc_rfsoc_top.slx
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utilities/soc_rfsoc_init.m
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@@ -40,13 +40,16 @@ PRI = 1/PRF;
% CW mode (bypass pulse generation) % CW mode (bypass pulse generation)
CwMode = true; CwMode = true;
% Counter mode (bypass pulse and CW generation)
CounterMode = true;
% Output gain % Output gain
pulseGenGain = 1; pulseGenGain = 1;
%% Software parameters %% Software parameters
% Signal generator update rate % Signal generator update rate
TsSW = 0.25; TsSW = 0.0025;
%% Simulation parameters %% Simulation parameters