Added documentation and updated README

README.md

@@ -4,11 +4,15 @@
 
 This project is based on the RFSoC SoC Blockset reference design, adapted as a prototype for a Radar Electronic Support Measures (R-ESM) receiver.
 
-### Current Status
+The system implements a high-throughput signal chain in the FPGA (PL) and performs frame-based processing in the processor (PS).
 
-- Tx subsystem: simple tone generator (to be replaced by LFM pulse generator)
+---
+
+## Current Status
+
+- Tx subsystem: LFM pulse generator (DDS-based, complex output)
 - Rx subsystem: fully functional channelizer pipeline (PFB-based)
-- PL → PS interface: AXI4-Stream + DMA working
+- PL → PS interface: AXI4-Stream + DMA operational
 - PS processing: frame-based algorithm (RMS + peak detection)
 
 ---
@@ -21,7 +25,7 @@ ADC → Channelizer (PFB, 512 bins)
 → AXI4-Stream (uint64)  
 → DMA (S2MM)  
 → PS Memory  
-→ Processor Algorithm (frame-based)
+→ Processor Algorithm  
 
 ---
 
@@ -37,48 +41,26 @@ ADC → Channelizer (PFB, 512 bins)
 
 ---
 
-## DMA (PL → PS)
+## 📚 Documentation
 
-- Data type: uint64
-- Frame size: 512
-- Buffers: 16
-- Memory: PS DDR
+### FPGA (PL)
 
-Each TLAST corresponds to one DMA frame.
+- [Tx Subsystem (Pulse Generator)](docs/pl_tx_subsystem.md)
+- [Rx Subsystem (Channelizer)](docs/pl_rx_subsystem.md)
+
+### Processor (PS)
+
+- [PS Subsystem](docs/ps_subsystem.md)
 
 ---
 
-## Processor (PS)
+## System Flow
 
-- Event-driven execution (triggered by DMA)
-- No task queueing
-- Frames may be dropped if processing is slower than input rate
+Tx → Rx → PS
 
----
-
-## Data Path in PS
-
-- Stream Read → uint64[512]
-- Bit extraction → real/imag
-- Conversion → complex vector
-- Processing → RMS + peak detection
-
----
-
-## Performance Notes
-
-- Bottleneck: unpacking + type conversion
-- PS cannot keep up with full-rate stream
-- Frames are skipped under load
-
----
-
-## FrFT Integration Plan
-
-- Replace Processor Algorithm with FrFT
-- Keep all other components unchanged
-- Input: complex single [512x1]
-- Accept dropped frames initially
+- Tx generates waveform  
+- Rx captures and channelizes  
+- PS processes frames  
 
 ---
 

docs/pl_rx_subsystem.md

@@ -0,0 +1,34 @@
+# 📡 PL Rx Subsystem (Channelizer)
+
+## Overview
+
+Implements PFB channelizer and FFT processing.
+
+---
+
+## Architecture
+
+ADC → PFB → FFT → Capture → FIFO → AXI → DMA
+
+---
+
+## Processing
+
+- 4096 MSPS input
+- Decimation 8
+- FFT 512 bins
+
+---
+
+## Output
+
+- AXI4-Stream
+- uint64 format
+- TLAST per frame
+
+---
+
+## 🔗 Related Components
+
+- [PL Tx Subsystem](pl_tx_subsystem.md)
+- [PS Subsystem](ps_subsystem.md)

docs/pl_tx_subsystem.md

@@ -0,0 +1,49 @@
+# 📡 PL Tx Subsystem (Pulse Generator)
+
+## Overview
+
+The Tx subsystem implements a pulse-based LFM chirp generator using a DDS/NCO architecture.
+
+---
+
+## Architecture
+
+TxPulseStart → pulse_gen_ctrl → tx_active → NCO → Output
+
+---
+
+## Chirp Generation
+
+Δφ[n] = Δφ[n−1] + step  
+φ[n]  = φ[n−1] + Δφ[n]
+
+---
+
+## Parameterization
+
+- Fc (center frequency)
+- B (bandwidth)
+
+Derived:
+f_start = Fc − B/2  
+step    = B / (N − 1)
+
+---
+
+## Pulse Timing
+
+|<------ PRI ------>|
+|<-- pulse -->| idle |
+
+---
+
+## Trigger
+
+Controlled via TxPulseStart (from PS subsystem)
+
+---
+
+## 🔗 Related Components
+
+- [PS Subsystem](ps_subsystem.md)
+- [PL Rx Subsystem](pl_rx_subsystem.md)

docs/ps_subsystem.md

@@ -0,0 +1,32 @@
+# 🧠 PS Subsystem
+
+## Overview
+
+Handles control and processing.
+
+---
+
+## Control
+
+- Writes parameters
+- Triggers Tx (TxPulseStart)
+
+---
+
+## Processing
+
+DMA → unpack → complex → RMS/peak
+
+---
+
+## Execution
+
+- Event-driven
+- Frame drops possible
+
+---
+
+## 🔗 Related Components
+
+- [PL Tx Subsystem](pl_tx_subsystem.md)
+- [PL Rx Subsystem](pl_rx_subsystem.md)

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