3 Commits

Author	SHA1	Message	Date
canisio	b2ce956f41	Multi-frame capture integrated into full design with trigger-controlled DPW; AXI stream (uint32 [4x1]) and DMA framing aligned; fixed FSM termination condition (no overflow); validated end-to-end (PL→DMA→PS) using counter input for multiple nFrames	2026-04-17 17:03:34 -03:00
canisio	ce87190fba	If sw side of AXI4-Stream to Software block is set to fixdt(128), frames appear to be arriving correctly on PS. However, reinterpretation is failing when using option "uint32"	2026-04-17 11:33:18 -03:00
canisio	cb56e78923	changed folder name for all testbench models	2026-04-17 08:31:14 -03:00