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• d8a9e026ff Added testbench for simulink model. Added f0 option to both testbenches main canisio 2026-03-30 16:01:46 -03:00
• 1613ae8ad9 Ran codegen for mex and tested. Working ok canisio 2026-03-30 11:44:31 -03:00
• 7b04d52204 Added frft functions towards codegen (c code on PS) canisio 2026-03-30 11:16:12 -03:00
• 30b31509c1 Updated README canisio 2026-03-30 09:30:16 -03:00
• 10644b0475 added README canisio 2026-03-27 18:41:29 -03:00
• 43f91b281b Tested on board. Running ok. Updated interface model and added shortcut to it. canisio 2026-03-27 17:52:13 -03:00
• 89ecf79e61 Added comment os PS system. Info from training says the time-driven tasks are all inside the processor block, except the event driven and the initialize canisio 2026-03-27 17:17:28 -03:00
• 13263f4f33 Removed one of the channels and respective beamforming on Tx and Rx. Simulation ok. Kept the read registers of the angles as placeholders for future use. canisio 2026-03-27 16:51:41 -03:00
• 81ca3ee48c Added renamed prj file canisio 2026-03-27 15:52:18 -03:00
• 2e297e7f07 Rename project and clean tracked files canisio 2026-03-27 15:51:00 -03:00
• 7c361a9608 Prepare to remove one of the channels. The idea is to transform the beamforming project in a simple wideband detector. canisio 2026-03-27 13:24:50 -03:00
• 584db6233c - Added utilities for frequency planning - Changed freq plane to: Fs 4096, int/dec 8X, Mixers 768 canisio 2026-03-27 12:50:10 -03:00
• d5bbdfb435 Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation canisio 2026-03-25 18:23:42 -03:00
• 89c8003f5a Added sw interface model (controls hardware running on board). canisio 2026-03-25 17:21:09 -03:00
• 7c1292ae5c Added startup function to project (setup HDL tool on it) canisio 2026-03-25 16:15:16 -03:00
• c86497656b Changed fs to 1024MSPS and added double-sided spectrum visualization. FFT Shifit with two selectors and one concatenate canisio 2026-03-24 18:10:26 -03:00
• ac2e7bcece Initial canisio 2026-03-24 12:44:45 -03:00