canisio
9a0404f1a9
4 dalay on the signals of bypass to align test counter to frame start. Appears to be working. Test on board.
2026-04-22 10:30:14 -03:00
canisio
4ad5c3c5ea
appear to be working with 4 daley after multi-frame capture. Problem is on visualization,
2026-04-21 16:19:43 -03:00
canisio
4b1b94c424
Added counter mode as input, real part = sample counter, imag part = frame counter. Reset on software trigger
2026-04-21 12:25:21 -03:00
canisio
78a7d1ae68
updated interface model. Still not working
2026-04-21 10:00:38 -03:00
canisio
7f369d8692
runs on the board. But capture is not in sync
2026-04-20 17:09:57 -03:00
canisio
286c464f5a
set SoCData as datatype again on the stream read inport (I dont know if this was the problem, but its working again)
2026-04-20 15:04:14 -03:00
canisio
b2ce956f41
Multi-frame capture integrated into full design with trigger-controlled DPW; AXI stream (uint32 [4x1]) and DMA framing aligned; fixed FSM termination condition (no overflow); validated end-to-end (PL→DMA→PS) using counter input for multiple nFrames
2026-04-17 17:03:34 -03:00
canisio
ce87190fba
If sw side of AXI4-Stream to Software block is set to fixdt(128), frames appear to be arriving correctly on PS. However, reinterpretation is failing when using option "uint32"
2026-04-17 11:33:18 -03:00
canisio
15f20619b1
MultiFrame camputre PL part integrated (no test, no PS)
2026-04-16 17:25:28 -03:00
canisio
88e9df3dbb
Multi-frame capture (trigger-controlled DPW) validated in testbench; added 128-bit packer replacing serializer, correct unpacking (SI reinterpret) and frame reconstruction verified (counter + PFB); implemented VALID gating (zero when idle) and AXI-aligned pipelining; nFrames parameterized in TB
2026-04-16 16:44:44 -03:00
canisio
2b8f8de030
Validation of multiframe on TBm_capture done.
2026-04-15 17:52:09 -03:00
canisio
9fd110f451
Replace serializer with 128-bit packer and add MultiFrameCapture (testbench)
...
Removed FIFO serializer and implemented 128-bit AXI packing (4 samples/beat)
Added initial MultiFrameCapture FSM
Validated with counter input
Sine/channelizer validation pending (frame interpretation update needed)
2026-04-14 17:56:57 -03:00
canisio
aad231b55a
AXI with 128 bits and no serializer appears to be working
2026-04-14 16:46:18 -03:00
canisio
d83006c50c
Added counter as input for the TBm_capture
2026-04-14 10:32:02 -03:00
canisio
5e5bba3ce6
Stable 16-bit Q1.15 Rx chain before AXI width upgrade
2026-04-14 09:25:01 -03:00
canisio
ccc6b9cd73
Validate 16-bit Q1.15 Rx chain (baseline, partial validation)
...
Standardized ADC/DAC and channelizer input to fixdt(1,16,15)
Rescaled channelizer output from sFix25_En23 to 16-bit complex
Verified channelizer path and spectrum behavior in full simulation
Bypass path and datatype tuning (coefficients/output) pending validation
2026-04-13 17:47:08 -03:00
canisio
4241699c3d
TBm_caputre. changed PFB internals and output datatype
2026-04-09 12:43:32 -03:00
canisio
d4e53a67ee
Stable single frame (512 samples) baseline before capture redesign
2026-04-09 09:27:44 -03:00
canisio
520a37f520
CW mode integrated to design
2026-04-08 15:00:47 -03:00
canisio
cd91e3066b
added CW mode (with LFM) to the chirp block (TB, not integrated yet)
2026-04-08 12:19:03 -03:00
canisio
5a3bc8891d
cleaned up log signals (still not working)
2026-04-07 09:26:50 -03:00
canisio
84b795203a
pulse generator integrated but not working
2026-04-06 16:16:42 -03:00
canisio
ada7e324cd
Fixed register address on "update parameters"
2026-04-06 15:15:55 -03:00
canisio
7813d9744c
Modified PS part and interface towards pulse generation integration
2026-04-06 12:26:06 -03:00
canisio
3c6ae0cfe9
finished organization of init funcions and parameters
2026-04-04 16:05:17 -03:00
canisio
eb14676581
Oganize preload and init functions and parameters (ongoing)
2026-04-04 15:16:58 -03:00
canisio
ac2e7bcece
Initial
2026-03-24 12:44:45 -03:00
