Created valid_out for conter input test

AXI4-S2Software>Main>Advanced>Interconnect: Data width (bits) changed to 128
2026-04-24 16:36:13 -03:00 · 2026-04-24 12:14:14 -03:00
5 changed files with 1 additions and 1 deletions
--- a/gm_soc_rfsoc_top_sw.slx
+++ b/gm_soc_rfsoc_top_sw.slx
--- a/referencedmodels/soc_rfsoc_fpga.slx
+++ b/referencedmodels/soc_rfsoc_fpga.slx
--- a/referencedmodels/soc_rfsoc_proc.slx
+++ b/referencedmodels/soc_rfsoc_proc.slx
--- a/soc_rfsoc_top.slx
+++ b/soc_rfsoc_top.slx
--- a/utilities/soc_rfsoc_init.m
+++ b/utilities/soc_rfsoc_init.m
@@ -49,7 +49,7 @@ pulseGenGain = 1;
 %% Software parameters
 % Signal generator update rate
-TsSW = 0.001;
+TsSW = 0.004;
 %% Simulation parameters
Author	SHA1	Message	Date
canisio	a7e710b603	Created valid_out for conter input test	2026-04-24 16:36:13 -03:00
canisio	c10736a5d7	AXI4-S2Software>Main>Advanced>Interconnect: Data width (bits) changed to 128	2026-04-24 12:14:14 -03:00