92 lines
1.9 KiB
Markdown
92 lines
1.9 KiB
Markdown
# 📡 RFSoC Channelizer + PS Processing (R-ESM Prototype)
|
|
|
|
## Overview
|
|
|
|
This project is based on the RFSoC SoC Blockset reference design, adapted as a prototype for a Radar Electronic Support Measures (R-ESM) receiver.
|
|
|
|
The system implements a high-throughput signal chain in the FPGA (PL) and performs frame-based processing in the processor (PS).
|
|
|
|
---
|
|
|
|
## Current Status
|
|
|
|
- Tx subsystem: LFM pulse generator (DDS-based, complex output)
|
|
- Rx subsystem: fully functional channelizer pipeline (PFB-based) or bypass
|
|
- PL → PS interface: AXI4-Stream + DMA operational
|
|
- PS processing: frame-based algorithm on a Data Process Window (DPW)
|
|
|
|
---
|
|
|
|
## System Architecture
|
|
|
|
Tx (PL)
|
|
→ Waveform Generator (LFM / CW / Pulsed)
|
|
→ DAC
|
|
→ RF Loopback / Input
|
|
|
|
Rx (PL)
|
|
→ ADC
|
|
→ Channelizer (PFB, 512 bins) / Bypass / Counter
|
|
→ Capture (frame control)
|
|
→ AXI4-Stream (128-bit, 4 samples/clock)
|
|
→ DMA (S2MM)
|
|
→ PS Memory
|
|
→ Processor Algorithm
|
|
|
|
Post Processing (PS)
|
|
→ Triggered Capture
|
|
→ Sample Unpacking (I/Q)
|
|
→ Data Reshaping → [FrameSize x nFrames x nTriggers]
|
|
→ Host Communication / Processing / Visualization
|
|
→ One DPW is a windows of FrameSize x nFrames samples
|
|
|
|
---
|
|
|
|
## Key Parameters
|
|
|
|
- ADC Sampling Rate: 4096 MSPS
|
|
- Decimation: 8
|
|
- Effective BW: 512 MHz
|
|
- Channels (FFT size): 512
|
|
- Samples per clock: 4
|
|
- FPGA clock: 128 MHz
|
|
- Frame size (PS): 512 samples
|
|
|
|
---
|
|
|
|
## 📚 Documentation
|
|
|
|
### FPGA (PL)
|
|
|
|
- [Tx Subsystem (Pulse Generator)](docs/pl_tx_subsystem.md)
|
|
- [Rx Subsystem (Channelizer)](docs/pl_rx_subsystem.md)
|
|
|
|
### Processor (PS)
|
|
|
|
- [PS Subsystem](docs/ps_subsystem.md)
|
|
|
|
---
|
|
|
|
## System Flow
|
|
|
|
Tx → Rx → PS
|
|
|
|
- Tx generates waveform
|
|
- Rx captures and channelizes
|
|
- PS processes frames
|
|
|
|
---
|
|
|
|
## Roadmap
|
|
|
|
1. Functional FrFT (PS)
|
|
2. Profiling
|
|
3. NEON optimization
|
|
4. Throughput tuning
|
|
5. PL acceleration
|
|
|
|
---
|
|
|
|
## Key Takeaway
|
|
|
|
First make it work end-to-end, then make it fast. |